PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 33

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 5-3:
 2010 Microchip Technology Inc.
WDPS<3:0>
WDTEN
MCLRE
LPT1OSC
PBADEN
PBADEN
CCP2MX
DEBUG
XINST
Note 1:
Bit Name
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG2H
CONFIG2H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG4L
CONFIG4L
Words
Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
MCLR Pin Enable bit
1 = MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR pin is disabled
Low-Power Timer1 Oscillator Enable bit
1 = Timer1 is configured for low-power operation
0 = Timer1 is configured for high-power operation
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
1 = PORTB A/D<4:0> and PORTB A/D<1:0> pins are configured as analog input 
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general 
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit 
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled 
PORTB A/D Enable bit
PORTB A/D Enable bit (PIC18FXX8X devices only)
channels on Reset
purpose I/O pins
Debug
(Legacy mode)
PIC18F2XXX/4XXX FAMILY
Description
(2)
DS39622L-page 33