PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 12

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2XXX/4XXX FAMILY
2.6
When the LVP Configuration bit is ‘1’ (see
“Single-Supply
Low-Voltage ICSP mode is enabled. As shown in
Figure
is entered by holding PGC and PGD low, placing a logic
high on PGM and then raising MCLR/V
In this mode, the RB5/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-13:
FIGURE 2-14:
DS39622L-page 12
MCLR/V
PGM
PGD
PGC
V
MCLR/V
V
PGM
PGD
PGC
DD
DD
2-13, Low-Voltage ICSP Program/Verify mode
Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
PP
PP
V
/RE3
/RE3
IH
Figure 2-14
ICSP
PGD = Input
V
PGD = Input
ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
IH
P15
V
P16
IH
shows the exit sequence.
Programming”),
P12
V
P18
IH
PP
/RE3 to V
Section 5.3
the
IH
.
command, PGC is cycled four times. The commands
2.7
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
2.7.1
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
needed for programming and verification are shown in
Table
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in
is shown Most Significant bit (MSb) first. The command
operand, or “Data Payload”, is shown as <MSB><LSB>.
Figure 2-15
20-bit command/operand to the device.
2.7.2
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 2-8:
TABLE 2-9:
Core Instruction
(Shift in16-bit instruction)
Shift Out TABLAT Register
Table Read
Table Read, Post-Increment
Table Read, Post-Decrement
Table Read, Pre-Increment
Table Write
Table Write, Post-Increment by 2
Table Write, Start Programming, 
Post-Increment by 2
Table Write, Start Programming
Command
1101
4-Bit
2-8.
Serial Program/Verify Operation
4-BIT COMMANDS
CORE INSTRUCTION
demonstrates how to serially present a
Description
Payload
3C 40
Data
COMMANDS FOR
PROGRAMMING
SAMPLE COMMAND
SEQUENCE
 2010 Microchip Technology Inc.
Table Write, 
post-increment by 2
Table
2-9. The 4-bit command
Core Instruction
Command
0000
0010
1000
1001
1010
1011
1100
1101
1110
1111
4-Bit