PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 15

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in Parameter D111 if
a Bulk Erase is to be executed. All other Bulk Erase
details, as described above, apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase”
“Modifying Code
FIGURE 3-2:
3.1.3
Regardless of whether high or low-voltage ICSP is used,
it is possible to erase one row (64 bytes of data), provided
the block is not code or write-protected. Rows are located
at static boundaries, beginning at program memory
address, 000000h, extending to the internal program
memory limit (see
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage
discharge of the memory array.
 2010 Microchip Technology Inc.
PGC
PGD
4-Bit Command
1
0
LOW-VOLTAGE ICSP BULK ERASE
ICSP ROW ERASE
2
0
3
1
Section 2.3 “Memory
4
Memory”.
1
P5
BULK ERASE TIMING
1
1
Data Payload
2
1
16-Bit
15 16
0
and
0
P5A
Maps”).
Section 3.2.1
4-Bit Command
1
0
2
0
PIC18F2XXX/4XXX FAMILY
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-Bit
If it is determined that a data EEPROM erase
(selected devices only, see
EEPROM
supply voltage below the Bulk Erase limit, follow the
methodology
EEPROM Programming”
The code sequence to Row Erase a PIC18F2XXX/
4XXX family device is shown in
flowchart, shown in
necessary to completely erase a PIC18F2XXX/4XXX
family device. The timing diagram that details the Start
Programming command and Parameters P9 and P10
is shown in
15 16
Note:
0
0
P5A
4-Bit Command
Programming”) must be performed at a
1
0
Figure
The TBLPTR register can point to any
byte within the row intended for erase.
2
0
described
3
0
3-5.
4
0
Figure
Erase Time
and write ‘1’s to the array.
in
P11
3-3, depicts the logic
Section 3.3
Section 3.3 “Data
DS39622L-page 15
Table
P10
Data Payload
16-Bit
3-3. The
1
n
2
“Data
n