PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2XXX/4XXX FAMILY
2.3
For PIC18FX6X0 devices, the code memory space
extends from 0000h to 0FFFFh (64 Kbytes) in four
16-Kbyte blocks. For PIC18FX5X5 devices, the code
memory space extends from 0000h to 0BFFFFh
(48 Kbytes) in three 16-Kbyte blocks. Addresses,
0000h through 07FFh, however, define a “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.
The size of the Boot Block in PIC18F2585/2680/4585/
4680 devices can be configured as 1, 2 or 4K words
(see
bits in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of Block 0.
FIGURE 2-3:
DS39622L-page 4
Note:
3FFFFFh
01FFFFh
000000h
200000h
Figure
*
Memory Maps
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
Unimplemented
2-3). This is done through the BBSIZ<1:0>
Code Memory
Configuration
Read as ‘0’
and ID
Space
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5X5/X6X0 DEVICES
11/10
Block 0
Block*
Boot
Unimplemented
(PIC18FX6X0)
Reads all ‘0’s
64 Kbytes
Block 2
Block 1
Block 3
Block 0
Block*
Boot
01
MEMORY SIZE/DEVICE
Block 0
Block*
Boot
00
TABLE 2-2:
BBSIZ<1:0>
PIC18F2515
PIC18F2525
PIC18F2585
PIC18F4515
PIC18F4525
PIC18F4585
PIC18F2610
PIC18F2620
PIC18F2680
PIC18F4610
PIC18F4620
PIC18F4680
Device
11/10
Block 0
Block*
Boot
(PIC18FX5X5)
Unimplemented
IMPLEMENTATION OF CODE
MEMORY
Reads all ‘0’s
48 Kbytes
Block 0
Block 1
Block 2
Block*
Boot
01
 2010 Microchip Technology Inc.
Code Memory Size (Bytes)
000000h-00BFFFh (48K)
000000h-00FFFFh (64K)
Block 0
Block*
Boot
00
000000h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
01FFFFh
Address
Range