JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet
JN5139/001,515
Specifications of JN5139/001,515
Related parts for JN5139/001,515
JN5139/001,515 Summary of contents
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Data Sheet: JN5139-001 and JN5139-Z01 IEEE802.15.4 and ZigBee Wireless Microcontrollers Overview The JN5139 is a low power, low cost wireless microcontroller suitable for IEEE802.15.4 and ZigBee applications. RISC processor, with a fully compliant 2.4GHz IEEE802.15.4 transceiver, 192kB of ROM, 96kB ...
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Introduction 1.1 Wireless Microcontroller 1.2 Wireless Transceiver 1.3 RISC CPU and Memory 1.4 Peripherals 1.5 Block Diagram 2 Pin Configurations 2.1 Pin Assignment 2.2 Pin Descriptions 2.2.1 Power Supplies 2.2.2 Reset 2.2.3 16MHz System Clock 2.2.4 Radio 2.2.5 Analogue ...
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Transmit 8.3.2 Reception 8.3.3 Auto Acknowledge 8.3.4 Beacon Generation 8.3.5 Security 8.4 Security Coprocessor 9 Digital Input/Output 10 Serial Peripheral Interface 11 Intelligent Peripheral Interface 11.1 Data Transfer Format 11.2 JN5139 (Slave) Initiated Data Transfer 11.3 Remote Processor (Master) ...
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Deep Sleep Mode 17 Electrical Characteristics 17.1 Maximum ratings 17.2 DC Electrical Characteristics 17.2.1 Operating Conditions 17.2.2 DC Current Consumption 17.2.3 I/O Characteristics 17.3 AC Characteristics 17.3.1 Reset 17.3.2 SPI Master Timing 17.3.3 Intelligent Peripheral (SPI Slave) Timing 17.3.4 ...
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Introduction The JN5139-001 and JN5139-Z01 are IEEE802.15.4 wireless microcontrollers that provide a fully integrated solution for applications using the IEEE802.15.4 and ZigBee standards in the 2.4 - 2.5GHz ISM frequency band [1]. They include all of the functionality required ...
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Peripherals The following peripherals are available on-chip: • Master SPI port with five select outputs • Two UARTs • Two programmable Timer/Counters with capture/compare facility • Two programmable Sleep Timers and a Tick Timer • Two-wire serial interface (compatible ...
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Block Diagram Tick Timer 32-bit RISC CPU Programmable Interrupt Controller From Peripherals RAM ROM 96kB 192kB VB_xx VDD1 Voltage Regulators VDD2 RESETN Reset Wakeup WT1 WT0 Clock XTALIN Generator XTALOUT COMP1M Comparator1 COMP1P COMP2M Comparator2 COMP2P DAC1 DAC1 DAC2 ...
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Pin Configurations DIO16/IP_DI 1 DIO17/CTS1/IP_SEL 2 VB_DIG2 3 DIO18/RTS1/IP_INT 4 DIO19/TXD1 5 DIO20/RXD1 6 VSS2 7 RESETN 8 VSS3 9 VSSS 10 XTALOUT 11 XTALIN 12 VB_SYN 13 VCOTUNE 14 Figure 2: 56-pin QFN Configuration (top view) Note: Please ...
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Pin Assignment Pin No Power supplies 3, 13, 15, 21 28, VB_DIG2, VB_SYN, VB_VCO, VB_RF, VB_A, 35, 40 VB_DIG1, VB_MEM 16, 49 VDD1, VDD2 7,9,10,39, PADDLE VSS2, VSS3, VSSS, VSS1, VSSA 8 RESETN 11, 12 XTALOUT, XTALIN 14 VCOTUNE ...
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Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 ...
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Analogue Peripheral 2.2.6 Digital Input/Output Digital I/O pins on the JN5139 can have signals applied higher than VDD2 (with the exception of pins DIO9 and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > ...
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CPU The CPU of the JN5139 is a 32-bit load and store RISC processor. It has been architected for three key requirements: • Low power consumption for battery powered applications • High performance to implement a wireless protocol at ...
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Memory Organisation This section describes the different memories found within the JN5139. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. © NXP Laboratories UK 2010 0xFFFFFFFF RAM ...
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ROM The ROM is 192K bytes in size, organized as 48k x 32-bit words and can be accessed by the CPU in a single clock cycle. The ROM contents include bootloader to allow external Flash memory contents to be ...
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OTP eFuse Memory The JN5139 contains 48-bytes of eFuse memory; this is one time programmable memory that is organised 32-bit words, 4 words are reserved by Jennic and 4 words are reserved for future use. The ...
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When bootloading program code from external serial memory, the JN5139 automatically accesses the encryption key to execute the decryption process. User program code does not need to handle any of the decryption process transparent process. With encryption ...
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System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5139. A 16MHz clock, generated by a crystal-controlled 16MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. ...
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External Clock An externally supplied 32kHz reference clock on the CLK32K input (DIO9) may be provided to the JN5139. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more ...
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Reset A system reset initialises the device to a predefined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5139 goes through is as follows. When power is applied, the ...
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If the application requires a power supply reset to be used, i.e. removing and then applying VDD important that the device decoupling capacitors are completely discharged (less than 0.4v) before the VDD is re-applied. Failure ...
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Interrupt System The interrupt system on the JN5139 is a hardware-vectored interrupt system. The JN5139 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt ...
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Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library. Further details of interrupts are provided ...
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Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, an O-QPSK modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standards-based wireless transceiver that transmits and ...
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Radio External components The VCO loop filter requires three external components and the IBIAS pin requires one external component as shown in Figure 15. These components should be placed close to the JN5139 pins and analogue ground. 330pF The ...
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ADO (DIO[12]) TX Active RX Active 1 Figure 17 Antenna Diversity ADO Signal for TX with Acknowledgement 8.2 Modem The Modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in ...
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Symbol detection and synchronization is performed using direct sequence correlation techniques in conjunction with searches for the Preamble and Start-of-Frame Delimiter (SFD) fields contained in the transmitted IEEE 802.15.4 Synchronization Header (SHR). Features are provided to support network channel selection ...
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During the passage of the bitstream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame. If using slotted access possible for ...
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Information such as the type of security operation to be performed and the encrypt/decrypt key to be used must also be provided. Processor Interface In-line Interface Figure 20: Security Coprocessor Architecture 28 AES Block AES Encrpytion Encoder Controller JN-DS-JN5139 1v9 ...
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Digital Input/Output There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the ...
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Throughout a sleep cycle the direction of the DIO, and the state of the outputs, is held. This is based on the resultant of the GPIO Data/ Direction registers and the effect of any enabled peripherals at the point of ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5139 and peripheral devices. The JN5139 operates as a master on the SPI bus and all other devices connected to the SPI are expected ...
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Slave 0 Slave 1 Flash User Memory Defined SPISEL0 Figure 23: Typical JN5139 SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5139 supports transfers at selectable data rates from 16MHz ...
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A transaction commences with the SPI bus being set to the correct configuration, and then the slave device is selected. Upon commencement of transmission ( bits) data is placed in the FIFO data buffer and clocked out, ...
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Intelligent Peripheral Interface The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor that requires a wireless peripheral example, the JN5139 may provide a complete JenNet wireless network interface ...
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If the data length is non-zero, the data in the JN5139 transmit memory buffer is sent, beginning at the start of the buffer. ...
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Timers 12.1 Peripheral Timer / Counters Two general-purpose timer / counter units are available that can be independently configured to operate in one of five modes. The timers have the following features: • 5-bit prescaler, divides system clock by ...
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An interrupt can be generated when the counter is equal to the value in either of the High or Low registers. The internal Output Enable (OE) signal enables or disables the timer output. The Timer 0 signals CK_GT, CAP and ...
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Counter / Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use timer the clock source is from the system clock, prescaled if required. The timer ...
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Timer / Counter Application Figure 31 shows an application of the JN5139 timers to provide closed loop speed control. Timer 0 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the ...
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Tick Timer The JN5139 contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system high-precision ...
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See Section 16 for further details on how they are used during sleep periods. Features include: • 32-bit down-counter • Optionally ...
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Serial Communications The JN5139 has two independent Universal Asynchronous Receiver / Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. Each interface performs serial-to-parallel conversion on incoming serial ...
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RTS (negated if the receive FIFO fill level is 15 and another character starts to be received, and asserted when the receive FIFO is read), and only transmits data when the incoming CTS is asserted. Software ...
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Two-Wire Serial interface The JN5139 includes an industry standard two-wire synchronous serial interface (SIF) that provides a simple and efficient method of data exchange between devices. The system operates as a master only and uses a serial data line ...
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The first byte of data transferred by the device after a start bit is the slave address. The JN5139 supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching ...
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Analogue Peripherals The JN5139 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors, switches and actuators. Chip Boundary VREF ADC1 ADC2 ADC3 ADC4 Temp Sensor COMP1P COMP1M COMP2P COMP2M DAC1 DAC2 ...
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Analogue to Digital Converter The 12-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, ...
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To facilitate averaging of the ADC values, which is a common practice in microcontrollers, a dedicated accumulator has been added, the user can define the accumulation to occur over 2,4 samples. The end of conversion interrupt can be ...
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Comparators The JN5139 contains two analogue comparators COMP1 and COMP2 that are designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level (common to both comparators) can be ...
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Power Management and Sleep Modes 16.1 Operating Modes Three operating modes are provided in the JN5139 that enable the system power consumption to be controlled to maximise battery life. • Active Processing • Sleep Mode • Deep Sleep Mode ...
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Whilst in CPU doze the current associated with the CPU drops, the RAM_FRACTION and ROM_FRACTION are both 0 and hence the base device current consumption drops to 2.85mA. 16.3 Sleep Mode The JN5139 enters sleep mode through software control. In ...
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Electrical Characteristics 17.1 Maximum ratings Exceeding these conditions may result in damage to the device. Parameter Device supply voltage VDD1, VDD2 Supply voltage at voltage regulator bypass pins VB_xxx Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RFP, RFM, Voltage ...
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DC Current Consumption VDD = 2.2 to 3.6V, -40 to +85º C 17.2.2.1 Active Processing Mode: Min CPU processing Radio transmit [boost mode] Radio receive [boost mode] The following current figures should be added to those above if the ...
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I/O Characteristics VDD = 2.2 to 3.6V, -40 to +85º C Parameter Min Internal DIO pull – resistors 24 31 Digital I/O High Input VDD2 x 0.7 (excludes DIO9 and DIO10) Digital I/O High Input for VDD2 ...
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VDD = 2.2 to 3.6V, -40 to +85º C Parameter Min External Reset pulse width (t ) RST External Reset threshold VDD2 x 0.7 voltage (V ) RST Internal Power-on Reset threshold voltage (V ) POT Power rise time (t ...
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Intelligent Peripheral (SPI Slave) Timing IP_SEL t sss IP_CLK IP_DI t lz IP_DO Figure 43: Intelligent Peripheral (SPI Slave) Timing Parameter Clock period Data setup time Data hold time Data invalid period Select set-up period Select hold period Select ...
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HIGH period of the SIF_CLK clock Set-up time for repeated START condition Data setup time SIF_D Rise Time SIF_D and SIF_CLK Fall Time SIF_D and SIF_CLK Set-up time for STOP condition Bus free time between a STOP and START condition ...
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Oscillator VDD = 2.2 to 3.6V, -40 to +85 ºC Parameter Min Current consumption of cell and counter logic 32kHz clock native -30% accuracy Calibrated 32kHz accuracy Variation with temperature Variation with VDD2 17.3.7 16MHz Crystal Oscillator VDD ...
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Bandgap Reference VDD = 2.2 to 3.6V, -40 to +85ºC Parameter Min Voltage 1.134 DC power supply rejection Temperature coefficient Point of inflexion 17.3.9 Analogue to Digital Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Min ...
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Digital to Analogue Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Resolution Current consumption Integral nonlinearity Differential nonlinearity Offset error Gain error Internal clock Output settling time to 0.5LSB Minimum Update time Output voltage swing Output ...
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Comparators VDD = 2.2 to 3.6V -40 to +85ºC Parameter Analogue response time (normal) Total response time (normal) including delay to Interrupt controller Analogue response time (low power) Hysteresis Vref (Internal) See Section 17.3.8 Bandgap Reference Common Mode input ...
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Radio parameters: 2.2-3.6V, +25ºC Parameter Min Receive sensitivity -92 Receive sensitivity -92.5 (boost) Maximum input signal Adjacent channel rejection -1 channel / +1 channel [CW Interferer] Alternate channel rejection [CW Interferer] Other in band rejection 2.4 to 2.4835 GHz, ...
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Parameter Min EVM [offset] Transmit Power Spectral Density 17.3.13.2 Radio parameters: 2.2-3.6V, -40ºC Parameter Min Receive sensitivity Maximum input signal Adjacent channel rejection -1 channel / +1 channel Alternate channel rejection Other in band rejection 2.4 to 2.4835 GHz, excluding ...
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Parameter Min EVM [offset] Transmit Power Spectral Density 17.3.13.3 Radio parameters: 2.2-3.6V, +85ºC Parameter Min Receive sensitivity Maximum input signal Adjacent channel rejection -1 channel / +1 channel Alternate channel rejection Other in band rejection 2.4 to 2.4835 GHz, excluding ...
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Parameter Min EVM [offset] Transmit Power Spectral Density Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 Note2 extra 4dB of ...
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Appendix A Mechanical and Ordering Information A.1 56pin QFN Package Drawing 66 JN-DS-JN5139 1v9 Controlling Dimension: mm millimetres Symbol Min. Nom. Max. A ------ ------ 0.9 A1 0.00 0.01 0.05 A2 ------ 0.65 0.7 A3 0.20 Ref. b 0.2 0.25 ...
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A.2 PCB Decal The following PCB decal is recommended; all dimensions are in millimetres (mm). For further detail please consult the Module Development Reference Manual JN-RM-2006, available to download from the Jennic Support web site (www.nxp.com/jennic/support) © NXP Laboratories UK ...
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A.3 Ordering Information The standard qualification for the JN5139 is Industrial Specification: -40ºC to +85ºC, packaged in a 56-pin QFN (Quad Flat No-leads) package. Ordering Code Format: JN5139/XXX ROM Variant XXX: 001 IEEE802.15.4 Z01 ZigBee Ordering Codes: Part Number Ordering ...
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A.4 Device Package Marking The diagram below shows the package markings for JN5139 devices. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the ...
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A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 56QFN package in the tape is as shown in Figure 45. Figure 46 shows the detailed dimensions of the tape used for 8x8mm 56QFN devices. ...
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A.5.2 Reel Information: 180mm Reel Surface Resistivity Between 10e Material High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked ...
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A.5.3 Reel Information: 330mm Reel Surface Resistivity Between 10e Material High Impact Polystyrene with Antistatic Additive All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Tape Width ...
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A.6 PCB Design and Reflow Profile PCB and land pattern designs are key to board level reliability, and Jennic strongly recommends that users follow the design rules listed in IPC-SM-782. For reflow profiles recommended to follow the reflow ...
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Appendix B Development Support B.1 Crystal Oscillator 16MHz Crystal Requirements Parameter Crystal Frequency Crystal Tolerance Crystal ESR Range (Rm) Crystal Load Capacitance Range (CL) Not all Combinations of Crystal Load Capacitance and ESR are valid refer to Section B.1.3 Recommended ...
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B.1.2 Crystal Load Capacitance The crystal load capacitance is the total capacitance seen at the crystal pins, from all sources. As the load capacitance (CL) affects the oscillation frequency by a process known as ‘pulling’, crystal manufacturers specify the frequency ...
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This can be used to give an equation for the required transconductance ≥ Example: Using typical parameters of equation above gives the required transconductance ( transconductance of 1.25mA/V The example and equation illustrate the trade-off that exists between ...
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Crystal Oscillator Transconductance Versus Supply Voltage 1.32 1.3 1.28 1.26 1.24 1.22 1.2 2.2 B.2 16MHz Oscillator The JN5139 contains the necessary on-chip components to build a 16 MHz reference oscillator with the addition of an external crystal resonator, two ...
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B.3 Applications Information B.3.1 Typical Application Schematic Two Wire Serial Port UART 1 I/O Line 1 CTS1 VB_DIG2 RTS1 Vcc C7 TXD1 R3 RXD1 VS S2 RESE T RESE TN C16 VS S3 C10 VS SS XTALOUT Y1 XTAL IN ...
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B.3.2 Reference Designs For customers wishing to integrate the JN5139 device directly into their system, Jennic provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae. These reference designs should be followed accurately to ...
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Appendix C Related Documents [1] IEEE Std 802.15.4-2003 IEEE Standard for Information technology – Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] JN-AN-1003 Boot Loader Operation [3] JN-AN-1062 ...
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Disclaimers The contents of this document are subject to change without notice. Jennic reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained herein. Information contained in this document regarding device applications ...
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Contact Details For the contact details of your local Jennic office or distributor, refer to the Jennic web site: 82 NXP Laboratories UK Ltd (Formerly Jennic Ltd) Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: ...