JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 57

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JN5139/001,515

Manufacturer Part Number
JN5139/001,515
Description
IC MCU 32BIT 56QFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of JN5139/001,515

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.3.5 Power Down and Wake-Up timings
Note: The 2.75ms time is from release of reset or the wakeup event to the CPU executing code. At this point if the
Flash is read there is an additional startup delay, as shown in the table.
© NXP Laboratories UK 2010
Wake up from Deep Sleep
(or reset)
Wake up from Sleep
(memory not held)
Wake up from Sleep
(Memory held)
Wake up from CPU Doze
mode
HIGH period of the SIF_CLK clock
Set-up time for repeated START condition
Data setup time SIF_D
Rise Time SIF_D and SIF_CLK
Fall Time SIF_D and SIF_CLK
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Noise margin at the LOW level for each
connected device (including hysteresis)
Noise margin at the HIGH level for each
connected device (including hysteresis)
Parameter
Min
2.75 + 0.5* program
size in kBytes
2.75 + 0.5* program
size in kBytes
2.75
0.2
JN-DS-JN5139 1v9
t
t
t
Typ
SU:STA
SU:DAT
SU:STO
t
t
HIGH
V
V
BUF
C
t
t
R
F
nh
nl
b
0.1VDD
0.2VDD
0.25
4.7
4
2
4
-
-
-
Max
1000
300
400
-
-
-
-
-
-
-
Unit
ms
ms
ms
µs
20+0.1Cb
20+0.1Cb
0.1VDD
0.2VDD
0.6
0.5
0.1
0.6
1.3
-
Assumes SPI clock to
external Flash is16MHz
Assumes SPI clock to
external Flash is16MHz
Notes
300
300
400
-
-
-
-
-
-
-
µs
µs
µs
ns
ns
µs
µs
pF
V
V
57

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