JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 50

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JN5139/001,515

Manufacturer Part Number
JN5139/001,515
Description
IC MCU 32BIT 56QFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of JN5139/001,515

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16 Power Management and Sleep Modes
16.1 Operating Modes
Three operating modes are provided in the JN5139 that enable the system power consumption to be controlled to
maximise battery life.
The variation in power consumption of the three modes is a result of having a series of power domains within the chip
that may be selectably powered on or off.
16.1.1 Power Domains
The JN5139 has the following power domains:
The current consumption figures for the different modes of operation of the device is given in section 17.2.2.
16.2 Active Processing Mode
Active processing mode in the JN5139 is where all of the application processing takes place. All of the peripherals
are available to the application as are options to actively enable or disable them to control power consumption; see
specific peripheral sections for details.
To further reduce power consumption, there is also the option to doze the CPU but keep the rest of the chip active;
this is particularly useful for radio transmit and receive operations, where the CPU operation is not required.
Whilst in Active processing mode there is the option to doze the CPU but keep the rest of the chip active; this is
particularly useful for radio transmit and receive operations, where the CPU operation is not required.
Whilst in Active processing mode the power consumption will vary based upon whether code is being executed out of
RAM or out of ROM, as the current consumption of RAM is lower than that of the ROM, so the calculation for
determining the typical current is made as follows.
where RAM_FRACTION + ROM_FRACTION =1. For example, with 80% code execution from the RAM and 20%
code execution from the ROM and CPU at 16MHz, the current is 9.7mA. See section 17.2.2.1 for further information
on active processing current consumption.
16.2.1 CPU Doze
Whilst in doze mode, CPU operation is stopped but the chip remains powered and the digital peripherals continue to
run. Doze mode is entered through software and is terminated by any interrupt request. Once the interrupt service
routine has been executed, normal program execution resumes. Doze mode uses more power than sleep and deep
sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop.
50
Active Processing
Sleep Mode
Deep Sleep Mode
VDD Supply Domain: supplies the wake-up timers and controller, DIO blocks, Comparators and 32kHz RC
oscillator. This domain is driven from the external supply (battery) and is always powered. The wake-up timers
and controller, and the 32kHz RC oscillator may be powered on or off in sleep mode through software control.
Digital Logic Domain: supplies the digital peripherals, CPU, ROM, Baseband controller, Modem and Encryption
processor. It is powered off during sleep mode.
Analogue Domain: supplies the ADC, DACs and the temperature sensor. It is powered off during sleep mode
and may be powered on or off in active processing mode through software control.
RAM Domain: supplies the RAM during sleep mode to retain the memory contents. It may be powered on or off
for sleep mode through software control.
Radio Domain: supplies the radio interface. It is powered during transmit and receive and controlled by the
baseband processor. It is powered off during sleep mode.
2.85mA + (RAM_FRACTION * 0.295mA/MHz) + (ROM_FRACTION * 0.958mA/MHz)
JN-DS-JN5139 1v9
© NXP Laboratories UK 2010

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