JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 12

• Manufacturer Part Number: JN5139/001,515
• Description: IC MCU 32BIT 56QFN
• Manufacturer: NXP Semiconductors

Specifications of JN5139/001,515

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3 CPU
The CPU of the JN5139 is a 32-bit load and store RISC processor. It has been architected for three key
requirements:
It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the
same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are
also mapped into this space.
The CPU contains a block of 32 32-bit General-Purpose (GP) registers together with a small number of special
purpose registers which are used to store processor state and control interrupt handling. The contents of any GP
register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations,
and signed and unsigned comparisons can be performed either between two registers and stored in a third, or
between registers and a constant carried in the instruction. Operations between general or special-purpose registers
execute in one cycle (16MHz) while those that access memory require a further cycle to allow the memory to
respond.
The instruction set manipulates 8, 16 and 32-bit data, stored in big-endian format; this means that programs can use
objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-
end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors,
and to execute in fewer clock cycles.
The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in
complex data structures is very efficient due to the provision of several addressing modes, together with the ability to
be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made
more efficient by using GP registers rather than pushing objects on the stack. The recommended programming
method for the JN5139 is by using C, which is supported by a software developer kit comprising a C compiler, linker
and debugger.
The CPU architecture also contains features that make the processor suitable for embedded, real-time applications.
In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the
processor.
Embedded applications require efficient handling of external hardware events. Exception processing (including reset
and interrupt handling) is enhanced by the inclusion of a number of special-purpose registers into which the PC and
status register contents are copied as part of the operation of the exception hardware. This means that the essential
registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the
processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler
to start executing in the next cycle.
To improve power consumption a number of power-saving modes are implemented in the JN5139, described more
fully in section 16 - Power Management and Sleep Modes. One of these modes is the CPU doze mode; under
software control, the processor can be shut down and on an interrupt will wake up to service the request.
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Low power consumption for battery powered applications
High performance to implement a wireless protocol at the same time as complex applications
Efficient coding of high-level languages such as C provided with the Jennic Software Developers Kit
JN-DS-JN5139 1v9
© NXP Laboratories UK 2010