JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 29

• Manufacturer Part Number: JN5139/001,515
• Description: IC MCU 32BIT 56QFN
• Manufacturer: NXP Semiconductors

Specifications of JN5139/001,515

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9 Digital Input/Output
There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a
selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device,
see section 2. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual module
sections for a full description of the alternate peripherals functions. Following a reset (and whilst the reset input is
held low), all peripherals are off and the DIO pins are configured as inputs with the internals pull-ups turned on.
When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin
can be controlled individually by setting the direction and then reading or writing to the pin.
The individual pull-up resistors, R
cycles. The pull-ups are generally configured once after reset depending on the external components and
functionality. For instance, outputs should generally have the pull-ups disabled. An input that is always driven should
also have the pull-up disabled.
When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable
transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is
sleeping, these interrupts become events that can be used to wake the device up. Equally the status of the interrupt
may be read. See section 16 Power Management and Sleep Modes for further details on sleep and wakeup.
The state of all DIO pins can be read, irrespective of whether the DIO is configured as an input or an output.
© NXP Laboratories UK 2010
Processor Bus
(Address, Data, Interrupts)
Counter/Timer 0
Counter/Timer 1
Data / Direction
2-Wire Serial
PU
Peripheral
Intelligent
Registers
Interface
SPI Port
UART 0
UART 1
RFTX
GPIO
, can also be enabled or disabled as needed and the setting is held through sleep
Figure 21: DIO Block Diagram
JN-DS-JN5139 1v9
SPISEL<4:0>
TIM0CK_GT
TIM1CK_GT
TIM0OUT
TIM1OUT
TIM0CAP
TIM1CAP
SIF_CLK
IP_CLK
IP_SEL
IP_INT
IP_DO
SIF_D
RFTX
IP_DI
RxD
RTS
CTS
RxD
RTS
CTS
TxD
TxD
DIO<20:0>
SPICLK, MOSI, MISO
SPISEL<0>
MUX
DIO<20:0>
Chip
Pins
29