A3930KJPTR-T Allegro Microsystems Inc, A3930KJPTR-T Datasheet - Page 12

• Manufacturer Part Number: A3930KJPTR-T
• Description: IC,Motor Controller,QFP,48PIN
• Manufacturer: Allegro Microsystems Inc

Specifications of A3930KJPTR-T

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Current - Output: 500mA
• Voltage - Supply: 5.5 V ~ 50 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 620-1289-2; A3930KJPTR-T

A3930
A3931
• Overtemperature This event pulls both fault flags low but
• Logic Fault: Hall Invalid The A3930 and the A3931 differ
• Short to Ground A short from any of the motor phase con-
• Short to Supply A short from any of the motor phase connec-
• Shorted Motor Winding A short across the motor phase
• Low Load Current The sense amplifier output is monitored
In addition to a monitor on VREG, the A3930/A3931 also
The Hx inputs have pull-up resistors to ensure that a fault condi-
monitors both the bootstrap charge voltage, to ensure sufficient
high-side drive, and the 5 V reference voltage at V5, to ensure
correct logical operation. If either of these fall below the lock-
out voltage level, the fault flags are set.
does not disable any circuitry. It is left to the user to turn off
the device to prevent overtemperature damage to the chip and
unpredictable device operation.
slightly in how they handle error conditions on the Hall inputs,
Hx. When all Hx are 1s, both devices evaluate this as an illegal
code, and they pull both fault flags, FFx, low and coast the mo-
tor. This action can be used, if desired, to disable all FET drives
under bridge or motor fault conditions. The Hall logic fault
condition is not latched, so if the fault occurs while the motor is
running, the external FETs will be reenabled, according to the
commutation truth table (table 2), when the Hx inputs become
valid.
as all 1s, described in the preceding paragraph. The A3931,
however, evaluates this as a prepositioning code, and does not
register it as a fault.
tion will be indicated in the event of an open connection to a
Hall sensor.
nections to ground is detected by monitoring the voltage across
the top FETs in each phase using the appropriate Sx pin and the
voltage at VDRAIN. This drain-source voltage is then compared
to the voltage on the VDSTH pin. If the drain source voltage
exceeds the voltage at the VDSTH pin, FF2 will be pulled low.
tions to the battery or VBB connection is detected by monitor-
ing the voltage across the bottom FETs in each phase using the
appropriate Sx pin and the LSS pin. This drain-source voltage
is then compared to the voltage on the VDSTH pin. If the drain
source voltage exceeds the voltage at the VDSTH pin, FF2 will
be pulled low.
winding is detected by monitoring the voltage across both the
top and bottom FETs in each phase. This fault will pull FF2 low.
independently to allow detection of a low load current. This can
When all Hx are 0s, the A3930 handles this in the same manner
and
Automotive 3-Phase BLDC Controller
Short Fault Operation Because motor capacitance may cause
the measured voltages to show a fault as the phase switches, the
voltages are not sampled until one t
nal FET is turned on.
If a short circuit fault occurs when ESF = 0, the external FETs
are not disabled by the A3930/A3931. Under some conditions,
some measure of protection will be provided by the internal cur-
rent limit but in many cases, particularly for a short to ground,
the current limit will provide no protection for the external
FETs. To limit any damage to the external FETs or the motor, the
A3930/A3931 can either be fully disabled by the RESET input
or all FETs can be switched off by pulling the COAST input low.
Alternatively, setting ESF = 1 will allow the A3930/A3931 to dis-
able the outputs as soon as the fault is detected. The fault will be
latched until any of the following conditions occur:
a phase commutation
RESET goes low
COAST goes low
This will allow a running motor to coast to the next phase
commutation without the risk of damage to the external power
MOSFETs.
Low Load Current Fault Operation No action is taken for
a low load current condition. If the low load occurs due to an
open circuit on a phase connection while the motor is running,
the A3930/A3931 will continue to commutate the motor phases
according to the commutation truth table, table 2.
In some cases, this will allow the motor to continue operating at
a much reduced performance. The low load condition is checked
during a commutation period and is only flagged at the next com-
mutation event. The flag is cleared at the end of any subsequent-
commutation period where no low load current fault is detected.
If the motor stalls or is stationary, then the remaining phase con-
nections will usually be insufficient to start rotating the motor. At
start-up or after a reset, the low load condition is flagged until the
first time the motor current exceeds the threshold value, V
This allows detection of a possible open phase from startup, even
if the motor is not able to start running.
Note that a low load current condition can also exist if the motor
being driven has no mechanical load.
be used to detect if an open load condition is present. If, during
a commutation period, the output from the sense amplifier does
not go above a minimum value, V
further action will be taken.
and MOSFET Driver
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
CSOL
DEAD
, FF1 will go low. No
interval after the exter-
CSOL
.
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