A3930KJPTR-T Allegro Microsystems Inc, A3930KJPTR-T Datasheet - Page 9

• Manufacturer Part Number: A3930KJPTR-T
• Description: IC,Motor Controller,QFP,48PIN
• Manufacturer: Allegro Microsystems Inc

Specifications of A3930KJPTR-T

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Current - Output: 500mA
• Voltage - Supply: 5.5 V ~ 50 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 620-1289-2; A3930KJPTR-T

A3930
A3931
In order to provide a known start-up position for the motor, an
optional prepositioning function is available in the A3931. When
the Hall inputs are all driven low (H1 = H2 = H3 = 0), the power
FETs in the A phase source current from the supply, and those in
both the B and C phases sink current. This forces the motor to
move to an unstable position midway between two detent points
and allows any start-up algorithm to ensure correct initial direc-
tion of rotation. Note that this is only available in the A3931. The
A3930 will indicate a logic fault when all Hall inputs are driven
low. The commutation truth table for these inputs is shown in
table 2. The inputs can also be driven directly from a microcon-
troller or similar external circuit.
Gate Drive
The A3930/A3931 is designed to drive external N-channel power
MOSFETs. They supply the large transient currents necessary to
quickly charge and discharge the gate capacitance of the external
FETs in order to reduce dissipation in the external FETs during
switching. The charge and discharge rate can be controlled using
external resistors in series with the connections to the gate of the
FETs.
RDEAD Cross-conduction is prevented by the gate drive circuits
which introduce a dead time, t
off and the complementary FET on. The dead time is derived
from the value of a resistor, RDEAD, connected between the
RDEAD pin and AGND. If RDEAD is connected to V5, t
defaults to 6 μs typical.
GLA, GLB, and GLC Low-side gate drive outputs for external
NMOS drivers. External series-gate resistors, RGATE, (as close
as possible to the NMOS gate) can be used to control the slew
rate seen at the power-driver gate, thereby controlling the di/dt
and dv/dt of the Sx outputs. Referring to table 2, GLx = 1 (high)
means that the upper half (PMOS) of the driver is turned on, and
that its drain will source current to the gate of the low-side FET
in the external motor-driving bridge. GLx = 0 (low) means that
the lower half (NMOS) of the driver is turned on, and that its
drain will sink current from the corresponding external FET gate
circuit to the LSS pin.
SA, SB, and SC Directly connected to the motor, these
terminals sense the voltages switched across the load. These
terminals are also connected to the negative side of the bootstrap
capacitors and are the negative supply connections for the
floating high-side drivers. The discharge current from the high-
side FET gate capacitance flows through these connections,
and
DEAD
, between switching one FET
DEAD
Automotive 3-Phase BLDC Controller
which should have low-impedance traces to the FET bridge.
GHA, GHB, and GHC High-side gate drive outputs for exter-
nal NMOS drivers. External series-gate resistors, RGATE, can
be used to control the slew rate seen at the power-driver gate,
thereby controlling the di/dt and dv/dt of the Sx inputs. Referring
to table 2, GHx = 1 (high) means that the upper half (PMOS) of
the driver is turned on, and that its drain will source current to the
gate of the high-side FET in the external motor-driving bridge.
GHx = 0 (low) means that the lower half (NMOS) of the driver
is turned on, and that its drain will sink current from the corre-
sponding external FET gate circuit to the respective Sx pin.
CA, CB, and CC High-side connections for the bootstrap
capacitors and positive supply for high-side gate drivers. The
bootstrap capacitors, CBOOTx, are charged to approximately
V
output swings high, the voltage on the Cx pin rises with the out-
put to provide the boosted gate voltage needed for the high-side
N-channel power MOSFETs.
VDRAIN High impedance sense input (Kelvin connection) to
the top of the external FET bridge. This input allows accurate
measurement of the voltage at the drain of the high-side FETs and
should be connected directly to the bridge, close to the drain con-
nections of the high-side FETs, with an independent trace.
LSS Low-side return path for discharge of the gate capacitors.
It is connected to the common sources of the low-side external
FETs through an independent low-impedance trace.
Logic Control Inputs
Additional logic-level inputs are provided to enable specific
features described below. These logic inputs all have a nominal
hysteresis of 500 mV to improve noise performance.
RESET Allows minimum current consumption from the VBB
supply. When RESET is low, all internal circuitry is disabled
including the V5 output. When coming out of sleep state, the
protection logic ensures that the gate drive outputs are off until
the charge pump reaches proper operating conditions. The charge
pump stabilizes in approximately 3 ms under nominal conditions.
RESET has an internal pull-down resistor, 50 kΩ typical.
However, to allow the A3930/A3931 to start-up without the
need for an external logic input, the RESET pin can be pulled
to the battery voltage with an external pull-up resistor. Because
RESET also has an internal clamp diode, 6 V typical, to limit the
input current, the value of the external pull-up resistor should be
REG
when the corresponding Sx terminal is low. When the Sx
and MOSFET Driver
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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