AM29LV800DB-70ED Spansion Inc., AM29LV800DB-70ED Datasheet - Page 21

• Manufacturer Part Number: AM29LV800DB-70ED
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.
• Series: AM29r

Specifications of AM29LV800DB-70ED

• Memory Size: 8Mbit
• Package/case: 48-TSOP
• Supply Voltage Max: 3V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Access Time, Tacc: 70nS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: See Table 5 for program command sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip
erase command sequence is initiated by writing
two unlock cycles, followed by a set-up com-
mand. Two additional unlock write cycles are
then followed by the chip erase command,
which in turn invokes the Embedded Erase algo-
rithm. The device does not require the system
to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is
not required to provide any controls or timings
during these operations. Table 5 shows the
address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note
that a hardware reset during the chip erase
operation immediately terminates the opera-
January 21, 2005 Am29LV800D_00_A4_E
Increment Address
Figure 1. Program Operation
in progress
Embedded
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
P R E L I M I N A R Y
Am29LV800D
No
tion. The Chip Erase command sequence should
be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the
erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. See “Write Operation Status” for infor-
m a t i o n o n t h e s e s t a t u s b i t s . W h e n t h e
Embedded Erase algorithm is complete, the
device returns to reading array data and
addresses are no longer latched.
Figure 1 illustrates the algorithm for the erase
operation. See the Erase/Program Operations
tables in “AC Characteristics” for parameters,
and to Figure 1 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The
sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up
command. Two additional unlock write cycles
are then followed by the address of the sector to
be erased, and the sector erase command. Table
5 shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to pre-
program the memory prior to erase. The
Embedded Erase algorithm automatically pro-
grams and verifies the sector for an all zero data
pattern prior to electrical erase. The system is
not required to provide any controls or timings
during these operations.
After the command sequence is written, a sector
erase time-out of 50 µs begins. During the time-
out period, additional sector addresses and
s ec tor e ra se com m a n ds m ay b e wri tte n.
Loading the sector erase buffer may be done in
any sequence, and the number of sectors may
be from one sector to all sectors. The time
between these additional cycles must be less
than 50 µs, otherwise the last address and
command might not be accepted, and erasure
may begin. It is recommended that processor
interrupts be disabled during this time to ensure
all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase
command is written. If the time between addi-
tional sector erase commands can be assumed
to be less than 50 µs, the system need not
monitor DQ3. Any command other than
Sector Erase or Erase Suspend during the
t im e- o u t p e r io d r es et s th e d e v ic e t o
reading array data. The system must rewrite
the command sequence and any additional
sector addresses and commands.
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