CS61880-IQZ Cirrus Logic Inc, CS61880-IQZ Datasheet - Page 26

• Manufacturer Part Number: CS61880-IQZ
• Description: IC Octal E1 Line Interface Unit
• Manufacturer: Cirrus Logic Inc

10. RECEIVER
The CS61880 contains eight identical receivers that
utilize an internal matched impedance technique
that provides for the use of a common set of exter-
nal components for 120
eration (Refer to
feature enables the use of a one stuffing option for
all E1 line impedances. The receivers can also be
configured to use different external resistors to
match the line impedance for E1 75
modes (Refer to
In hardware mode, the CBLSEL pin is used to se-
lect the proper line impedance (75
either internal or external line impedance matching
mode.
In host mode, each receiver’s line impedance is se-
lected individually via the
ID Register (10h)
and bits[3:0] and the LEN[3:0] bits of the
Length Data Register (11h)
page 38). The INT_EXTB bit of the
Data Register (11h)
page 38) is used to select between internal or exter-
nal line impedance matching modes for all eight
channels. The CBLSEL pin is not used in host
mode.
The CS61880 receiver provides all of the circuitry
to recover both data and clock from the data signal
input on RTIP and RRING. The matched imped-
ance receiver is capable of recovering signals with
12 dB of attenuation (referenced to 2.37 V or 3.0 V
nominal) while providing superior return loss. In
addition, the timing recovery circuit along with the
jitter attenuator provide jitter tolerance that far ex-
ceeds jitter specifications (Refer to
page
The recovered data and clock are output from the
CS61880 on the RPOS/RDATA, RNEG and
RCLK pins. These pins output the data in one of
three formats: bipolar, unipolar, or RZ. The CLKE
26
57).
Figure 17 on page
(See Section 14.17 on page 38)
Figure 16 on page
(See Section 14.18 on
(E1), and 75
Line Length Channel
(See Section 14.18 on
51).
or 120 ) and
Line Length
Figure 19 on
or E1 120
50). This
Line
op-
pin is used to configure RPOS/RDATA and
RNEG, so that data is valid on either the rising or
falling edge of RCLK. Refer to the CLKE pin de-
scription on
10.1 Bipolar Output Mode
Bipolar mode provides a transparent clock/data re-
covery for applications in which the line decoding
is performed by an external framing device. The re-
covered clock and data are output on RCLK,
RNEG and RPOS.
10.2 Unipolar Output Mode
In unipolar mode, the CS61880 decodes the recov-
ered data with either HDB3 or AMI line decoding.
The decoded data is output on the RPOS/RDATA
pin. When bipolar violations are detected by the de-
coder, the RNEG/BPV pin is asserted “high”. This
pin is driven “high” for one RCLK period for every
bipolar violation that is not part of the zero substi-
tution rules. Unipolar mode is entered by holding
the TNEG pin “high” for more than 16 TCLK cy-
cles.
In hardware mode, the HDB3/AMI encoding/de-
coding is activated via the CODEN pin.
In host mode, Bit 4 of the
ID Register (10h)
is used to select the encoding/decoding for all chan-
nels.
10.3 RZ Output Mode
In this mode the RTIP and RRING inputs are sliced
to data values that are output on RPOS and RNEG
pins. This mode is used in applications that have
clock recovery circuitry external to the device. To
support external clock recovery, the RPOS and
RNEG outputs are XORed and output as RCLK.
This mode is entered when MCLK is tied high. The
polarity of the RPOS/RNEG data are controlled by
the CLKE pin. Refer to the CLKE pin description
on
page 13
for CLKE settings.
page 13
(See Section 14.17 on page 38)
for CLKE settings.
Line Length Channel
CS61880
DS450PP3