CS61880-IQZ Cirrus Logic Inc, CS61880-IQZ Datasheet - Page 35

• Manufacturer Part Number: CS61880-IQZ
• Description: IC Octal E1 Line Interface Unit
• Manufacturer: Cirrus Logic Inc

14. REGISTER DESCRIPTIONS
14.1 Revision/IDcode Register (00h)
14.2
14.3 Remote Loopback Register (02h)
14.4
14.5 LOS Status Register (04h)
14.6
DS450PP3
[7:4]
[3:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
BIT
BIT
BIT
BIT
BIT
BIT
Analog Loopback Register (01h)
TAOS Enable Register (03h)
DFM Status Register (05h)
DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to “1” when it detects a short circuit in channel
TAOE 7-0 A “1” in bit n of this register turns on the TAOS generator in channel n. Register bits default
LOSS 7-0 Register bit n is read as “1” when LOS is detected on channel n. Register bits default to
ALBK 7-0
RLBK 7-0
REVI 7-4
REVI 3-0
NAME
NAME
NAME
NAME
NAME
NAME
n. Register bits default to 00h after power-up or reset.
Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0000.
(Refer to
Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61880 Revision A = 0000.
These bits are subject to change with the revision of the device (Refer to
(IDR)
Enables analog loopbacks. A “1” in bit n enables the loopback for channel n. Refer to
Loopback
to 00h after power-up or reset.
Enables remote loopbacks. A “1” in bit n enables the loopback for channel n. Refer to
MODE
00h after power-up or reset.
to 00h after power-up or reset.
00h after power-up or reset.
(See Section 16.3 on page 47).
(See Section 13 on page 32) for a complete explanation. Register bits default to
Device ID Register (IDR)
(See Section 12.2 on page 29) for a complete explanation. Register bits default
(See Section 16.3 on page 47).
Description
Description
Description
Description
Description
Description
Device ID Register
CS61880
Analog
HOST
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