CS61880-IQZ Cirrus Logic Inc, CS61880-IQZ Datasheet - Page 33

• Manufacturer Part Number: CS61880-IQZ
• Description: IC Octal E1 Line Interface Unit
• Manufacturer: Cirrus Logic Inc

bidirectional I/O port, SDI and SDO may be tied to-
gether.
As illustrated in
R/W bit, address field, and two reserved bits. The
R/W bit specifies if the current register access is a
read (R/W = 1) or a write (R/W = 0) operation. The
address field specifies the register address from
0x00 to 0x1f.
13.3 Parallel Port Operation
Parallel port host mode operation is selected when
the MODE pin is high. In this mode, the CS61880
register set is accessed using an 8-bit, multiplexed
bidirectional address/data bus D[7:0]. Timing over
the parallel port is independent of the transmit and
receive system timing.
The device is compatible with both Intel and Mo-
torola bus formats. The Intel bus format is selected
when the INTL/MOT pin is high and the Motorola
bus format is selected when the INTL/MOT pin is
low. In either mode, the interface can have the ad-
dress and data multiplexed over the same 8-bit bus
or on separate busses. This operation is controlled
with the MUX pin; MUX = 1 means that the paral-
lel port has its address and data multiplexed over
the same bus; MUX = 0 defines a non-multiplexed
bus. The timing for the different modes are shown
DS450PP3
CLKE=0
SCLK
SDO
SDI
CS
R/W
Figure
0
12, the ACB consists of a
0
Address/Command Byte
Figure 12. Serial Read/Write Format (SPOL = 0)
0
0
1
0
0
in
Figure
Multiplexed Intel and Motorola modes are shown
in
read or write is initiated by writing an address byte
to D[7:0]. The device latches the address on the
falling edge of ALE(AS). During a read cycle, the
register data is output during the later portion of the
RD or DS pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD
transitions high in Intel timing or DS transitions
high in Motorola timing. During a write cycle, val-
id write data must be present and held stable during
the WR or DS pulses.
Non-multiplexed Intel and Motorola modes are
shown in
Figure
by the DS, RD or WR pin. Data is latched into or
out of the part using the rising edge of the DS, WR
or RD pin. Raising CS ends the cycle.
In Intel mode, the RDY output pin is normally in a
high impedance state; it pulses low once to ac-
knowledge that the chip has been selected, and high
again to acknowledge that data has been written or
read. In Motorola mode, the ACK pin performs a
similar function; it drives high to indicate that the
address has been received by the part, and goes low
again to indicate that data has been written or read.
Figure
Figure
D0
D0
29,
31. The CS pin initiates the cycle, followed
D1
D1
28,
Figure
28,
Figure
Figure
D2
D2
Figure
Data Input/Output
30,
29,
D3
D3
26,
Figure 31
26,
Figure
Figure 25
D4
D4
Figure
D5
D5
30,
and
and
25,
D6
D6
Figure 32
Figure
CS61880
Figure
Figure
D7
D7
32.
27. A
and
27,
33