CS61880-IQZ Cirrus Logic Inc, CS61880-IQZ Datasheet - Page 40

• Manufacturer Part Number: CS61880-IQZ
• Description: IC Octal E1 Line Interface Unit
• Manufacturer: Cirrus Logic Inc

14.26 AWG Enable Register (19h)
14.27 Reserved Register
14.28 Reserved Register (1Bh)
14.29 Reserved Register (1Ch)
14.30 Reserved Register (1Dh)
14.31 Bits Clock Enable Register (1Eh)
14.32 Reserved Register (1Fh)
14.33 Status Registers
The following Status registers are read-only:
Status Register (04h)
page 35),
40
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
BIT
BIT
BIT
BIT
BIT
BIT
BIT
AWGN 7-0
RSVD 7-0
RSVD 7-0
RSVD 7-0
RSVD 7-0
RSVD 7-0
BITS 7-0
DFM Status Register (05h)
NAME
NAME
NAME
NAME
NAME
NAME
NAME
The AWG enable register is used for selecting the source of the customized transmission
pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output
pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the
ROM is selected for transmission on channel n. (Refer to
(See Section 15 on page 42). Register bits default to 00h after power-up or reset.
Writing a “1” to bit n in this register changes channel n to a stand-alone timing recovery unit
used for G.703 clock recovery. (Refer to
(BITS) CLOCK MODE
recovery function). Register bits default to 00h after power-up or reset.
(See Section 14.5 on
(1Ah)
(See Sec-
(See Section 8 on page 23) for a better description of the G.703 clock
LOS
tion 14.6 on page 35) and
(13h)
CS61880 generates an interrupt on the INT pin any
time an unmasked status register bit changes.
Description
Description
RESERVED
Description
RESERVED
Description
RESERVED
Description
RESERVED
Description
Description
RESERVED
BUILDING INTEGRATED TIMING SYSTEMS
(See Section 14.20 on page 38). The
Arbitrary Waveform Generator
AIS Status Register
CS61880
DS450PP3