CS61880-IQZ Cirrus Logic Inc, CS61880-IQZ Datasheet - Page 37

• Manufacturer Part Number: CS61880-IQZ
• Description: IC Octal E1 Line Interface Unit
• Manufacturer: Cirrus Logic Inc

14.14 LOS/AIS Mode Enable Register (0Dh)
14.15 Automatic TAOS Register (0Eh)
14.16 Global Control Register (0Fh)
DS450PP3
[7:0]
[7:0]
[1:0]
BIT
BIT
BIT
[7]
[6]
[5]
[4]
[3]
[2]
JASEL [1:0]
AWG Auto-
Increment
LAME 7-0 Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; setting bit n to “0”
ATAO 7-0 Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected.
LENGTH
RAISEN
CODEN
NAME
NAME
NAME
RSVD
JACF
FIFO
enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after
power-up or reset.
This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,
encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for
all eight channels. Register bits default to 00h after power-up or reset.
The AWG Auto-Increment bit indicates whether to auto-increment the
Register (17h)
the phase samples address portion of the address register increments after each read or
write access. This bit must be set before any bit in the AWG Enable register is set, if this
function is required.
On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.
Line encoding/decoding Selection
Jitter Attenuator FIFO length Selection
Jitter Attenuator Corner Frequency Selection
These bits select the position of the Jitter Attenuator.
Register bits default to 00h after power-up or reset.
0 = Disabled
1 = Enabled
0 = HDB3
1 = AMI
0 = 32 bits
1 = 64 bits
0 = 1.25 Hz
1 = 2.50 Hz
JASEL 1
Table 11. Jitter Attenuator Position Selection
0
0
1
1
(See Section 14.24 on page 39) after each access. Thus, when this bit is set,
JASEL 0
0
1
0
1
RESERVED (This bit must be set to 0.)
Transmit Path
Receive Path
Description
Description
Description
POSITION
Disabled
Disabled
AWG Phase Address
CS61880
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