MT48LC16M16A2P-75 IT:D Micron Technology Inc, MT48LC16M16A2P-75 IT:D Datasheet - Page 67

• Manufacturer Part Number: MT48LC16M16A2P-75 IT:D
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2P-75 IT:D

• Density: 256 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 38: WRITE – DQM Operation
Burst Read/Single Write
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
Note:
t RCD
t CK
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
T1
NOP
1. For this example, BL = 4.
Disable auto precharge
Enable auto precharge
t CMS
t CL
t DS
Column m
WRITE
T2
Bank
D
t CMH
IN
t DH
t CH
T3
NOP
67
t DS
T4
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
IN
t DH
t DS
256Mb: x4, x8, x16 SDRAM
T5
NOP
D
IN
t DH
© 1999 Micron Technology, Inc. All rights reserved.
NOP
T6
WRITE Operation
NOP
T7
Don’t Care