M29DW128G70NF6E

Manufacturer Part NumberM29DW128G70NF6E
DescriptionP7ED TSOP56 DUAL BANK
ManufacturerNUMONYX
M29DW128G70NF6E datasheet
 
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M29DW128G
During program or erase operations the memory will continue to use the program/erase
supply current, I
CC3
3.5
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when RP is at V
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs.
3.6
Automatic standby
Automatic standby allows the memory to achieve low power consumption during read mode.
After a read operation, if CMOS levels (V
inactive for t
AVQV
supply current is reduced to the standby supply current, I
characteristics). The data inputs/outputs will still output data if a bus read operation is in
progress.
The power supplier of data bus, V
circuits connected with data bus) when the memory enters automatic standby.
Table 4.
Bus operations
(1)
Operation
E
G
Bus Read
V
V
IL
IL
Bus Write
V
V
IL
IH
Standby
V
X
IH
Output Disable
X
V
IH
Reset
X
X
1. X = V
or V
.
IL
IH
2. To write the four outermost parameter blocks (first two and last two), V
, for program or erase operations until the operation completes.
. The power consumption is reduced to the
IL
± 0.3 V) are used to drive the bus and the bus is
CC
+ 30 ns or more, the memory enters automatic standby where the internal
, can have a null consumption (depending on load
CCQ
W
RP
V
/WP
PP
V
V
X
IH
IH
(2)
V
V
X
IL
IH
X
V
X
IH
V
V
X
IH
IH
X
V
X
IL
PP
Bus operations
(see
Table 22: DC
CC2
Address inputs
Data inputs/outputs
A22-A0
DQ15-DQ0
Cell address
Data output
Command address
Data input
X
Hi-Z
Address
Hi-Z
X
Hi-Z
/WP must be equal to V
.
IH
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