P80C31SBPN NXP Semiconductors, P80C31SBPN Datasheet - Page 17

• Manufacturer Part Number: P80C31SBPN
• Description: MCU 8-Bit 80C 80C51 CISC ROMLess 3.3V/5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P80C31SBPN

• Package: 40PDIP
• Device Core: 80C51
• Family Name: 80C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Ram Size: 128 Byte
• Program Memory Type: ROMLess
• Operating Temperature: 0 to 70 °C
• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage Range: 2.7V To 5.5V
• Core Size: 8 Bit
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The 80C31 and 80C32 have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 7.
NOTES:
2000 Aug 07
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
IPH.x
PRIORITY BITS
0
0
1
1
SOURCE
BIT
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
SP
X0
T0
X1
T1
T2
Interrupt Table
IE (0A8H)
IP.x
0
1
0
1
SYMBOL
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
POLLING PRIORITY
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
EA
7
1
2
3
4
5
6
—
6
ET2
5
Figure 10. IE Registers
REQUEST BITS
ES
4
TF2, EXF2
RI, TI
TP0
TF1
IE0
IE1
17
ET1
3
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
EX1
2
HARDWARE CLEAR?
N (L)
ET0
N (L) Y (T)
1
1
Y
Y
N
N
Y (T)
EX0
0
2
80C31/80C32
VECTOR ADDRESS
Product specification
SU00571
0BH
1BH
2BH
03H
13H
23H