P80C31SBPN NXP Semiconductors, P80C31SBPN Datasheet - Page 8

• Manufacturer Part Number: P80C31SBPN
• Description: MCU 8-Bit 80C 80C51 CISC ROMLess 3.3V/5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P80C31SBPN

• Package: 40PDIP
• Device Core: 80C51
• Family Name: 80C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Ram Size: 128 Byte
• Program Memory Type: ROMLess
• Operating Temperature: 0 to 70 °C
• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Digital Ic Case Style: DIP
• Supply Voltage Range: 2.7V To 5.5V
• Core Size: 8 Bit
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle Mode
In idle mode (see Table 2), the CPU puts itself to sleep while all of
the on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return V
the minimum specified operating voltages before the Power Down
Mode is terminated.
Table 2. External Pin Status During Idle and Power-Down Modes
2000 Aug 07
Idle
Idle
Power-down
Power-down
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
MODE
PROGRAM MEMORY
External
External
Internal
Internal
CC
ALE
1
1
0
0
to
8
PSEN
For the 80C31 or 80C32, either a hardware reset or external
interrupt can be used to exit from Power Down. Reset redefines all
the SFRs but does not change the on-chip RAM. An external
interrupt allows both the SFRs and the on-chip RAM to retain their
values. WUPD (AUXR1.3–Wakeup from Power Down) enables or
disables the wakeup from power down with external interrupt.
Where:
To properly terminate Power Down the reset or external interrupt
should not be executed before V
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 or INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
For the 80C31, wakeup from power down is always enabled.
Design Consideration
ONCE
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 80C31/32 is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
possibility of an unexpected write when Idle is terminated by reset,
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
1
1
0
0
WUPD = 0 Disable
WUPD = 1 Enable
Mode
PORT 0
Float
Float
Data
Data
PORT 1
Data
Data
Data
Data
CC
is restored to its normal
80C31/80C32
PORT 2
Address
Data
Data
Data
Product specification
PORT 3
Data
Data
Data
Data