WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 155

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
Note:
Note:
Note:
Note:
10.2.1.3.14 Receive Interrupt Absolute Delay Timer- RADV (0x0282C; RW)
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
PTHRESH is used to control when a prefetch of descriptors is considered. This threshold
refers to the number of valid, unprocessed receive descriptors the chip has in its on-
chip buffer. If this number drops below PTHRESH, the algorithm considers pre-fetching
descriptors from host memory. This fetch does not happen however unless there are at
least HTHRESH valid descriptors in host memory to fetch.
HTHRESH should be given a non-zero value when ever PTHRESH is used.
WTHRESH controls the write back of processed receive descriptors. This threshold
refers to the number of receive descriptors in the on-chip buffer which are ready to be
written back to host memory. In the absence of external events (explicit flushes), the
write back occurs only after at least WTHRESH descriptors are available for write back.
Possible values:
GRAN = 1 (descriptor granularity):
PTHRESH = 0...31
WTHRESH = 0...31
HTHRESH = 0...31
GRAN = 0 (cache line granularity):
PTHRESH = 0...3 (for 16 descriptors cache line - 256 bytes)
WTHRESH = 0...3
HTHRESH = 0...4
For any WTHRESH value other than zero, the packet and absolute timers must get a
non-zero value for WTHRESH feature to take affect.
Since the default value for write-back threshold is one, the descriptors are normally
written back as soon as one cache line is available. WTHRESH must contain a non-zero
value to take advantage of the write-back bursting capabilities of the MAC.
If the packet delay timer is used to coalesce receive interrupts, it ensures that when
receive traffic abates, an interrupt is generated within a specified interval of no
receives. During times when receive traffic is continuous, it might be necessary to
ensure that no receive remains unnoticed for too long an interval. This register might
be used to ENSURE that a receive interrupt occurs at some pre-defined interval after
the first packet is received.
When this timer is enabled, a separate absolute countdown timer is initiated upon
successfully receiving each packet to system memory. When this absolute timer
expires, pending receive descriptor write backs are flushed and a receive timer
interrupt is generated.
15:0
31:16
Bits
RW
RO
Type
0x0
0x0
Reset
Receive Absolute Delay Timer. Receive absolute delay timer measured in
increments of 1.024 ms (0b = disabled).
Reserved. Reads as 0b.
Description
148