WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 44

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.4.1.1
7.4.1.1.1
37
Advanced Power Management Wake Up
Advanced Power Management Wakeup or APM Wakeup was previously known as Wake
on LAN (WoL). The basic premise is to receive a broadcast or unicast packet with an
explicit data pattern, and then to assert a signal to wake up the system or issue an in-
band PM_PME message (if configured to).
At power up, if the 82577’s wake up functionality is enabled, the APM Enable bits from
the NVM are written to the 82577 by the Intel
Enable (APME) bits of the Wakeup Control (WUC) register. These bits control the
enabling of APM wake up.
When APM wake up is enabled, the 82577 checks all incoming packets for Magic
Packets. See
To enable APM wake up, programmers should write a 1b to bit 10 in register 26 on page
0 PHY address 01, and then the station address to registers 27, 28, 29 at page 0 PHY
address 01. The order is mandatory since registers RAL0[31:0] and RAH0[15:0] are
updated with a corresponding value from registers 27, 28, 29, if the APM WoL Enable
bit is set in register 26. The Address Valid bit (bit 31 in RAH0) is automatically set with
a write to register 29, if the APM WoL Enable bit is set in register 26. The APM Enable
bit (bit 0 in the WUC) is automatically set with a write to register 29, if the APM WoL
Enable bit is set in register 26.
Once the 82577 receives a matching magic packet, it:
APM wake up is supported in all power states and only disabled if a subsequent NVM
read results in the APM Wake Up bit being cleared or software explicitly writes a 0b to
the APM Wake Up (APM) bit of the WUC register.
Link Status Change
When the LSCWO bit (bit 5 in the WUC register) is set, wake up is generated if all of the
following conditions are met:
When the 82577 detects a link status change it:
When the LSCWO bit is set, wake up is never generated on link status change if either
APM wake up is disabled or the LSCWE bit is cleared. In this case, the LNKC bit (bit 0)
in the Wake up Filter Control (WUFC) register is read as zero, independent of the value
written to it.
• Sets the Magic Packet Received bit in the WUS register.
• Initiates the Intel
• APM wake up is enabled (APME bit is set in the WUC register)
• The LSCWE bit (bit 4) is set in the WUC register
• Link status change is detected
• Sets the Link Status Changed (LNKC) bit (bit 0) in the WUS register.
• Initiates the Intel
message.
Section 7.4.1.3.1.4
®
®
5 Series Express Chipset wake up event through an in-band
5 Series Express Chipset wake up event.
for a definition of Magic Packets.
®
5 Series Express Chipset to the APM
82577 GbE PHY—Device Functionality