WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 93

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
Table 69.
Wake Up Status – WUS PHY Address 01, Page 800, Register 3
This register is used to record statistics about all wake up packets received. Note that
packets that match multiple criteria might set multiple bits. Writing a 1b to any bit
clears that bit.
This register is not cleared when PHY reset is asserted. It is only cleared when internal
power on reset is de-asserted or when cleared by the software device driver.
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RO
RWC
RWC
RO
RWC
RWC
RWC
RWC
Attribute
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit(s)
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Initial
Value
LNKC
Link status changed
MAG
Magic packet received
EX
Directed exact packet received. The packet’s address matched one of the 7 pre-
programmed exact values in the Receive Address registers.
MC
Directed multicast packet received. The packet was a multicast packet that was
hashed to a value that corresponded to a 1-bit in the multicast table array .
BC
Broadcast packet received.
IPv4 request packet received.
IPV4
Directed IPv4 packet received.
IPV6
Directed IPv6 packet received.
Reserved, read as 0b.
FLX4
Flexible filter 4 match.
FLX5
Flexible filter 5 match.
Reserved.
FLX0
Flexible filter 0 match.
FLX1
Flexible filter 1 match.
FLX2
Flexible filter 2 match.
FLX3
Flexible filter 3 match.
Description
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