WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 160

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
10.2.1.3.22 Shared Receive Address Low - SHRAL[n] (0x05438 + 8*n (n=0…3); RW)
10.2.1.3.23 Shared Receive Address High 0…2 - SHRAH[n] (0x0543C + 8*n (n=0…2);
153
AV determines whether this address is compared against the incoming packet. AV is
cleared by a master (software) reset.
ASEL enables the MAC to perform special filtering on receive packets.
The first receive address register (RAR0) is also used for exact match pause frame
checking (DA matches the first register). Therefore RAR0 should always be used to
store the individual Ethernet MAC address of the adapter.
After reset, if the NVM is present, the first register (Receive Address register 0) is
loaded from the IA field in the NVM, its Address Select field is 00b, and its Address
Valid field is 1b. If no NVM is present the Address Valid field is 0b. The Address Valid
field for all of the other registers is zero.
RW)
15:0
17:16
18
30:19
31
31:0
15:0
17:16
18
30:19
31
Bits
Bits
Bits
RW
RW
RW
RO
RW
RW
RW
RO
RW
RO
RW
Type
Type
Type
X
X
0b
0x0
See as
follows
X
X
00b
0b
0x0
0b
Reset
Reset
Reset
82577 GbE PHY—Intel
Receive Address High (RAH). The upper 16 bits of the 48-bit Ethernet address n
(n=0, 1…6). RAH 0 is loaded from word 2 in the NVM.
Address Select (ASEL). Selects how the address is to be used. Decoded as follows:
00b = Destination address (must be set to this in normal mode).
01b = Source address.
10b = Reserved.
11b = Reserved.
VMDq output index (VIND). Defines the VMDq output index associated with a
receive packet that matches this MAC address (RAH and RAL).
Reserved. Reads as 0b. Ignored on write.
Address Valid (AV). Cleared after master reset. If the NVM is present, the Address
Valid field of the Receive Address Register 0 is set to 1b after a software or PCI
reset or NVM read.
This bit is cleared by master (software) reset.
Receive Address Low (RAL). The lower 32 bits of the 48-bit Ethernet address n
(n=0…3).
Receive Address High (RAH). The upper 16 bits of the 48-bit Ethernet address n
(n=0…3).
Address Select (ASEL). Selects how the address is to be used. 00b means that it is
used to decode the destination MAC address.
VMDq output index (VIND). Defines the VMDq output index associated with a
receive packet that matches this MAC address (RAH and RAL).
Reserved. Reads as 0b. Ignored on write.
Address valid (AV). When this bit is set, the relevant RAL,RAH are valid (compared
against the incoming packet).
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description