WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 94

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 70.
Table 71.
Note:
87
Receive Address Low – RAL PHY Address 01, Page 800, Registers 16-17 +
4*n
1. While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6.
Receive Address High – RAH PHY Address 01, Page 800, Registers 18-19 +
4*n
1. While “n” is the exact unicast/Multicast address entry and it is equals to 0,1,…6
AV determines whether this address is compared against the incoming packet. AV is
cleared by a master (software) reset.
ASEL enables the 82577 to perform special filtering on receive packets.
RAR0 should always be used to store the individual Ethernet MAC address of the
Network Interface Card (NIC).
After reset, if the NVM is present, the first register (Receive Address Register 0) is
loaded from the IA field in the NVM, its Address Select field is 00b, and its Address
Valid field is 1b. If no NVM is present the Address Valid field is 0b. The Address Valid
field for all of the other registers are 0b.
RW
RW
RW
RO
RW
Attribute
Attribute
1
1
(n=0…6)
(n=0…6)
15:0
17:16
30:18
31
31:0
Bit(s)
Bit(s)
X
X
0x00
See
Desc.
Initial
0
Value
Initial
Value
Receive Address High (RAH)
The upper 16 bits of the 48-bit Ethernet address n (n=0, 1…6). RAH 0 is loaded
from word 0x2 in the NVM.
Address Select (ASEL)
Selects how the address is to be used and is decoded as follows:
00b = Destination address (must be set to this in normal mode).
01b = Source address.
10b = Reserved.
11b = Reserved.
Address valid (AV)
Cleared after master reset. If the NVM is present, the Address Valid field of
Receive Address Register 0 is set to one after a software or PCI reset or NVM
read.
This bit is cleared by a master (software) reset.
Reserved, reads as 0b and ignored on writes.
Receive Address Low (RAL)
The lower 32 bits of the 48-bit Ethernet address n (n=0, 1…6). RAL 0 is loaded
from words 0x0 and 0x1 in the NVM.
82577 GbE PHY—Programmer’s Visible State
Description
Description