XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet
XR16L570IL24-F
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XR16L570IL24-F Summary of contents
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MAY 2007 GENERAL DESCRIPTION The XR16L570 (L570 1.62 to 5.5 volt Universal Asynchronous Receiver and Transmitter (UART) with 5 volt tolerant inputs and a reduced pin count software compatible to industry standard ST16C580, ST16C650A, XR16C850 and ...
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... SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE (24- IGURE ACKAGE AND VCC 24-pin QFN ORDERING INFORMATION P N ART UMBER XR16L570IL24 XR16L570IL32 QFN P ) PIN ACKAGE DSR RI# 27 IOR# VCC 28 GND IOW CLK PwrSave ACKAGE 24-pin QFN 32-pin QFN 2 REV. 1.0 ...
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REV. 1.0.1 PIN DESCRIPTIONS Pin Descriptions 24-QFN 32-QFN N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE Pin Descriptions 24-QFN 32-QFN N T AME YPE CD UART Carrier-Detect (active low) or general purpose input. This input should ...
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REV. 1.0.1 1.0 PRODUCT DESCRIPTION The XR16L570 (L570 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the ST16C580 device and additionally offers Power-Save to isolate the data bus interface during Sleep mode. ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. ...
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REV. 1.0.1 2.2 5-Volt Tolerant Inputs The L570 can accept inputs when operating at 3.3V, 2.5V or 1.8V. But note that if the L570 is operating at 2.5V or below, its V OH serial transceiver that is ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.8 Crystal or External Clock Input The L570 includes an on-chip oscillator in the 32-QFN package (XTAL1 and XTAL2) to generate a clock when a crystal is connected between ...
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REV. 1.0.1 2.9 Programmable Baud Rate Generator The L570 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit (bit-7) in the MCR register. This bit selects the prescaler to divide ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7 DEFAULT 100 400 600 2400 1200 ...
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REV. 1.0 IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock 2.10.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.11.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the ...
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REV. 1.0.1 2.12 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE F 11. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin ...
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REV. 1.0.1 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the L570 will halt transmission (TX) as soon as ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.17 Infrared Mode The L570 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared ...
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REV. 1.0.1 2.18 Sleep Mode with Wake-Up Interrupt and Power-Save Feature The L570 supports low voltage system designs, hence, a sleep mode with wake-up interrupt and Power-Save feature is included to reduce power consumption when the device is not actively ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.19 Internal Loopback The L570 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. ...
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REV. 1.0.1 3.0 UART INTERNAL REGISTERS The L570 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The complete register set is shown on Table 5 T A2,A1,A0 A DDRESSES 0 0 ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE . T 6: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit-7 0 ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable XON1 WR Bit ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L570 in the FIFO polled ...
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REV. 1.0.1 • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from low to high. SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 23 XR16L570 ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an ...
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REV. 1.0 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset ...
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REV. 1.0.1 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This ...
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REV. 1.0.1 MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and MCR[5]: Xon-Any Enable • Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default). ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE LSR[4]: Receive Break Flag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was a logic 0 for at ...
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REV. 1.0.1 MSR[3]: Delta CD# Input Flag Since the 24-QFN package of the L570 does not have the CD# modem input, this bit has functionality only in internal loopback mode when the CD bit (MSR[7]) can be controlled via the ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 4.15 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see are selected, ...
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REV. 1.0.1 EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match exists, ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE T 11: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM and DLL Bits 15-0 = 0x0001. Resets upon power up only and not when only the ...
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REV. 1.0.1 DC ELECTRICAL CHARACTERISTICS U : TA= -40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER V Clock Input Low Level ILCK V Clock Input High Level IHCK V Input Low Voltage IL V Input High Voltage IH V Output ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE AC ELECTRICAL CHARACTERISTICS U : TA= -40 NLESS OTHERWISE NOTED S YMBOL - Crystal Oscillator Frequency OSC External Clock Frequency* CLK External Clock Low/High Time* T Address Setup Time ...
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REV. 1.0.1 AC ELECTRICAL CHARACTERISTICS U : TA= -40 NLESS OTHERWISE NOTED S YMBOL - Crystal Oscillator Frequency OSC External Clock Frequency* CLK External Clock Low/High Time* T Address Setup Time AS T Address Hold Time AH T Chip Select ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE DATA RATE CHARACTERIZATION -40 PERATING EMPERATURE ANGE P ARAMETER Supply Voltage, VCC Input High Voltage, V Input Low Voltage, V External Clock/Oscillator Frequency ...
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REV. 1.0 IGURE LOCK IMING CLK EXTERNAL CLOCK F 15 IGURE ODEM NPUT UTPUT IOW# RTS# Change of state CTS# INT IOR# SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE F 16 IGURE ATA US EAD IMING A0- A2 Address T AS CS# IOR# T RDV D0- IGURE ATA ...
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REV. 1.0 IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT IOR# (Reading data out of RHR IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE F 20 IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR IOR# (Reading data out of RX FIFO) F ...
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REV. 1.0.1 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE PACKAGE DIMENSIONS (24 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
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... Updated QFN package dimensions drawing to show minimum "k" parameter. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16L570 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM (24- IGURE ACKAGE AND IN UT ...
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SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.0.1 4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24 4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 24 4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... ABLE NTERRUPT OURCE ...