XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 10

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
O
2.10
2.10.1
2.10.2
UTPUT
MCR Bit-7=1
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
Transmitter Operation in non-FIFO Mode
Transmit Holding Register (THR) - Write Only
O
UTPUT
T
MCR Bit-7=0
ABLE
(
DEFAULT
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
3: T
)
YPICAL DATA RATES WITH A
Clock (Decimal)
D
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
16x
D
10
IVISOR FOR
Clock (HEX)
14.7456 MH
900
180
C0
0C
60
30
18
06
04
02
01
16x
V
Z EXTERNAL CLOCK
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
V
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
D
E
REV. 1.0.1
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)