XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 7

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The L570 can accept up to 5V inputs when operating at 3.3V, 2.5V or 1.8V. But note that if the L570 is
operating at 2.5V or below, its V
serial transceiver that is operating at 5V. Note that the XTAL1 (CLK) pin is not 5V tolerant.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
in the device.
The XR16L570 provides a Device Identification code and a Device Revision code. To read the identification
code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now
reading the content of the DLM will provide 0x01 to indicate XR16L570 and reading the content of DLL will
provide the revision of the part; for example, a reading of 0x01 means revision A.
The L570 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad
register (SPR).
Beyond the general 16C550 features and capabilities, the L570 offers enhanced feature registers (EFR, Xon1,
Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in
REGISTERS” on page
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR16L570. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
The interrupt output changes according to the operating mode and enhanced features setup.
Table 2
through 21.
2.2
2.3
2.4
2.5
2.6
2.7
INT Pin
INT Pin
5-Volt Tolerant Inputs
Device Hardware Reset
Device Identification and Revision
Internal Registers
DMA Mode
INT Output
below summarize the operating behavior for the transmitter and receiver. Also see Figures
Table
0 = one byte in THR
1 = THR empty
0 = no data
1 = 1 byte
11). An active pulse of longer than 40 ns duration will be required to activate the reset function
FCR B
19.
IT
(FIFO D
-0 = 0 (FIFO D
FCR B
T
OH
ABLE
T
ABLE
may not be high enough to meet the requirements of the V
IT
ISABLED
-0 = 0
1: INT P
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
2: INT P
ISABLED
)
IN
IN
O
)
O
PERATION FOR
PERATION
7
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
0 = FIFO below trigger level
1 = FIFO above trigger level
F
OR
T
RANSMITTER
R
ECEIVER
FCR B
“Section 3.0, UART INTERNAL
IT
(FIFO E
-0 = 1 (FIFO E
FCR B
IT
NABLED
-0 = 1
NABLED
)
IH
XR16L570
of a CPU or a
)
Table 1
and
18