XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 46

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
GENERAL DESCRIPTION .................................................................................................1
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................5
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................6
3.0 UART INTERNAL REGISTERS ...........................................................................................................19
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................21
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE .............................................................................................................................................. 6
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7
2.3 DEVICE HARDWARE RESET .......................................................................................................................... 7
2.4 DEVICE IDENTIFICATION AND REVISION ..................................................................................................... 7
2.5 INTERNAL REGISTERS ................................................................................................................................... 7
2.6 DMA MODE ....................................................................................................................................................... 7
2.7 INT OUTPUT ..................................................................................................................................................... 7
2.8 CRYSTAL OR EXTERNAL CLOCK INPUT ..................................................................................................... 8
2.9
2.10 TRANSMITTER ............................................................................................................................................. 10
2.11 RECEIVER .................................................................................................................................................... 11
2.12
2.13
2.14
2.15
2.16
2.17 INFRARED MODE ........................................................................................................................................ 16
2.18
2.19
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 21
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 21
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................... 21
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 21
F
F
F
T
T
F
F
F
T
F
F
F
F
F
T
F
F
T
T
IGURE
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ....................................................................................... 10
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 10
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 11
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 12
2.18.1 SLEEP MODE ........................................................................................................................................................... 17
2.18.2 POWER-SAVE FEATURE ........................................................................................................................................ 17
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 21
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 22
PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................ 9
AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................ 13
AUTO RTS HYSTERESIS ............................................................................................................................ 13
AUTO CTS FLOW CONTROL ..................................................................................................................... 13
AUTO XON/XOFF (SOFTWARE) FLOW CONTROL .................................................................................. 15
SPECIAL CHARACTER DETECT ............................................................................................................... 15
SLEEP MODE WITH WAKE-UP INTERRUPT AND POWER-SAVE FEATURE ........................................ 17
INTERNAL LOOPBACK .............................................................................................................................. 18
1: INT P
2: INT P
3: T
4: A
5: UART INTERNAL REGISTERS .................................................................................................................................... 19
6: INTERNAL REGISTERS DESCRIPTION. S
1. B
2. P
3. XR16L570 T
4. T
5. E
6. B
7. T
8. T
9. R
10. R
11. A
12. I
13. I
.....................................................................................................................................................1
YPICAL DATA RATES WITH A
UTO
YPICAL
RANSMITTER
RANSMITTER
LOCK
ACKAGE AND
XTERNAL
AUD
ECEIVER
NFRARED
NTERNAL
................................................................................................................................................1
UTO
ECEIVER
IN
IN
X
R
ON
D
O
O
RTS
ATE
C
IAGRAM
PERATION FOR
PERATION
/X
RYSTAL CONNECTIONS
O
C
L
OFF
T
O
G
PERATION IN NON
LOCK
OOP
AND
YPICAL
RANSMIT
PERATION IN
ENERATOR AND
O
O
.................................................................................................................................2
P
PERATION IN NON
PERATION IN
(S
IN
............................................................................................................................................................. 1
CTS F
B
C
OFTWARE
O
ACK
F
ONNECTION FOR
D
UT
OR
ATA
D
................................................................................................................................................. 18
(24-
ATA
T
LOW
R
RANSMITTER
ECEIVER
B
FIFO
14.7456 MH
) F
PIN
US
E
FIFO
C
-FIFO M
P
NCODING AND
TABLE OF CONTENTS
LOW
ONTROL
I
RESCALER
QFN P
NTERCONNECTIONS
AND
..................................................................................................................................... 8
-FIFO M
.................................................................................................................................. 7
AND
C
E
A
ONTROL
............................................................................................................................. 7
XTENDED
ODE
UTO
ACKAGE
O
F
Z EXTERNAL CLOCK
LOW
PERATION
....................................................................................................................... 9
ODE
.................................................................................................................... 12
RTS F
R
HADED BITS ARE ENABLED WHEN
ECEIVE
............................................................................................................... 15
C
.............................................................................................................. 11
).............................................................................................................. 2
ONTROL
D
ATA
LOW
....................................................................................................... 14
........................................................................................................ 6
I
D
R
ATA
C
ATE
M
ONTROL
ODE
D
............................................................................................ 8
.......................................................................................... 10
ECODING
..................................................................................... 11
M
ODE
.......................................................................... 16
....................................................................... 12
EFR B
IT
-4=1.......................................... 20
xr
REV. 1.0.1