XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 20

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
.
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 0 0
0 0 1
T
ABLE
DREV
N
DVID
MCR
MSR
RHR
DLM
THR
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
6: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
Global
FIFOs
Pres-
B
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
Bit-7
IT
0/
0/
0
-7
RX FIFO
IR Mode
RTS Int.
Enabled
ENable
Trigger
Enable
Set TX
THR &
FIFOs
Empty
Break
B
Input
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
RI#
IT
0/
0/
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
TX FIFO
Set Par-
XonAny
Xoff Int.
Enable
Source
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Bit-5
INT
ity
IT
0/
0/
0/
0/
0
-5
20
TX FIFO
Internal
Source
Trigger
Enable
Enable
Break
Sleep
Mode
Parity
Loop-
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
back
Bit-4
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
0
-4
S
HADED BITS ARE ENABLED WHEN
RX Fram-
INT Out-
ing Error
Stat. Int.
Modem
Source
(OP2#)
Enable
Enable
Enable
Enable
Mode
Parity
B
Delta
DMA
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
put
IT
0
-3
RX Line
(OP1#)
Enable
Source
IR RX
Reset
Parity
Invert
B
FIFO
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
0
-2
Enable
Source
Control
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
FIFO
Word
Delta
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
0
-1
EFR B
Source
Control
Enable
Enable
Length
Output
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
1
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
DLM=0x00
DLL=0x00
C
LCR[7]=0
LCR[7]=1
LCR[7]=1
REV. 1.0.1
OMMENT