XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 26

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select (Legacy)
This bit has no function and should be left at ’0’.
FCR[5:4]: Transmit FIFO Trigger Select
(’00’ = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(’00’ = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
4.7
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Line Control Register (LCR) - Read/Write
B
FCR
IT
0
0
1
1
-7
B
FCR
IT
0
1
0
1
-6
T
ABLE
B
FCR
IT
0
0
1
1
8: T
-5
BIT-1
RANSMIT AND
0
0
1
1
BIT
FCR
0
1
0
1
-4
T
RIGGER
1 (default)
R
BIT-0
R
ECEIVE
0
1
0
1
14
ECEIVE
4
8
L
EVEL
26
FIFO T
T
RIGGER
Table 8
1 (default)
T
RANSMIT
W
14
RIGGER
4
8
ORD LENGTH
5 (default)
L
EVEL
below shows the selections. EFR bit-4 must
Table 8
6
7
8
L
16C580 and 16L580 compati-
ble.
16C550, 16C580, 16L580,
16C554, 16C2550 and 16C2552
compatible
EVEL
shows the selections.
S
ELECTION
C
OMPATIBILITY
REV. 1.0.1