XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 12

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
F
F
2.11.1
IGURE
IGURE
Receive Data
Byte and Errors
9. R
10. R
16 bytes by 11-bit
Receive Holding Register (RHR) - Read-Only
16X Clock
ECEIVER
ECEIVER
wide
FIFO
16X Clock
and Errors
Data Byte
O
Receive
O
PERATION IN NON
PERATION IN
Receive Data Shift
Register (RSR)
Data FIFO
LSR bits
Receive
Receive
Tags in
FIFO
Error
Data
4:2
-FIFO M
Receive Data Shift
AND
Register (RSR)
Holding Register
Receive Data
A
ODE
UTO
Validation
FIFO Trigger=8
Data falls to
Data Bit
Data fills to
(RHR)
RX FIFO trigger level selected at 8 bytes
Example
14
RTS F
4
12
:
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Validation
Data Bit
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
C
ONTROL
RHR Interrupt (ISR bit-2)
M
Receive Data Characters
ODE
Receive Data Characters
RXFIFO1
RXFIFO1
REV. 1.0.1