NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet
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... Intel 82801DB I/O Controller Hub 4 (ICH4) Datasheet May 2002 Document Number: 290744-001 ...
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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries ...
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... Timers Based on 82C54 — System timer, refresh request, speaker tone output ® The Intel 82801DB ICH4 may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. ® ...
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... AC’97 Codec(s) 82801DB ICH4 LAN Connect GPIO Firmware Hub(s) LPC Interface Firmware Hubs (1-8) Super I/O Super I/O Othe ASIC Other ASICs r s (Optional) Memory Power Management Clock Generators Clock Generators System Management (TCO) 2 SMBus/I C PCI Bus ® Intel 82801DB ICH4 Datasheet ...
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... Functional Description 5.1 Hub Interface to PCI Bridge (D30:F0)............................................................67 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 ® Intel 82801DB ICH4 Datasheet ...........................................................................................................27 ..............................................................................................37 .....................................................................................67 PCI Bus Interface..............................................................................67 PCI-to-PCI Bridge Model ..................................................................68 IDSEL to Device Number Mapping ...................................................68 SERR# Functionality.........................................................................68 Parity Error Detection........................................................................70 Standard PCI Bus Configuration Mechanism ...................................71 PCI Dual Address Cycle (DAC) Support ...
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... Interrupt Handling ........................................................................... 113 Interrupt Mapping............................................................................ 113 APIC Bus Functional Description.................................................... 114 PCI Message-Based Interrupts....................................................... 121 Processor System Bus Interrupt Delivery ....................................... 122 Start Frame..................................................................................... 125 Data Frames ................................................................................... 125 Stop Frame ..................................................................................... 125 Specific Interrupts Not Supported via SERIRQ............................... 126 ® Intel 82801DB ICH4 Datasheet ...
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... Processor Interface Signals ............................................................130 5.11.2 Dual-Processor Designs .................................................................132 5.11.3 Speed Strapping for Processor.......................................................134 5.12 Power Management (D31:F0)......................................................................135 5.12.1 Intel 5.12.2 System Power Planes.....................................................................137 5.12.3 Intel 5.12.4 SMI#/SCI Generation......................................................................137 5.12.5 Dynamic Processor Clock Control ..................................................139 5.12.6 Sleep States....................................................................................141 5 ...
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... BCC—Base-Class Code Register (LAN Controller—B1:D8:F0)..... 255 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ....... 255 PMLT—PCI Master Latency Timer Register (LAN Controller—B1:D8:F0) ........................................................... 256 Register (LAN Controller—B1:D8:F0)............................................. 256 (LAN Controller—B1:D8:F0) ........................................................... 257 ....................................................... 251 ® Intel 82801DB ICH4 Datasheet ...
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... PBUS_NUM—Primary Bus Number Register 8.1.11 SBUS_NUM—Secondary Bus Number Register 8.1.12 SUB_BUS_NUM—Subordinate Bus Number Register ® Intel 82801DB ICH4 Datasheet (LAN Controller—B1:D8:F0) ...........................................................258 (LAN Controller—B1:D8:F0) ...........................................................259 (LAN Controller—B1:D8:F0) ...........................................................259 (LAN Controller—B1:D8:F0) ...........................................................260 (LAN Controller— ...
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... SCC—Sub-Class Code Register (LPC I/F—D31:F0) ..................... 295 BCC—Base-Class Code Register (LPC I/F—D31:F0) ................... 295 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................. 295 (LPC I/F—D31:F0) .......................................................................... 298 (LPC I/F—D31:F0) .......................................................................... 299 (LPC I/F—D31:F0) .......................................................................... 300 ................................................ 291 ® Intel 82801DB ICH4 Datasheet ...
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... Intel 82801DB ICH4 Datasheet (LPC I/F—D31:F0) ..........................................................................300 (LPC I/F—D31:F0) ..........................................................................304 (LPC I/F—D31:F0) ..........................................................................305 (LPC I/F—D31:F0) ..........................................................................306 (LPC I/F—D31:F0) ..........................................................................306 (LPC I/F—D31:F0) ..........................................................................307 (LPC I/F—D31:F0) ..........................................................................308 (LPC I/F— ...
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... TCO1_DAT_IN—TCO Data In Register ......................................... 372 TCO1_DAT_OUT—TCO Data Out Register................................... 372 TCO1_STS—TCO1 Status Register............................................... 373 TCO2_STS—TCO2 Status Register............................................... 374 TCO1_CNT—TCO1 Control Register............................................. 375 TCO2_CNT—TCO2 Control Register............................................. 376 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ..................... 376 ............................................................. 383 ® Intel 82801DB ICH4 Datasheet ...
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... SID — Subsystem ID (USB—D29:F0/F1/F2) .................................403 11.1.13 INTR_LN—Interrupt Line Register (USB—D29:F0/F1/F2) .............404 11.1.14 INTR_PN—Interrupt Pin Register (USB—D29:F0/F1/F2) ..............404 11.1.15 USB_RELNUM—USB Release Number Register ® Intel 82801DB ICH4 Datasheet (IDE—D31:F1) ................................................................................387 (IDE—D31:F1) ................................................................................387 (IDE D31:F1)...................................................................................388 (IDE D31:F1)...................................................................................388 (IDE— ...
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... EHCI—D29:F7) ..................................................................... 423 (USB EHCI—D29:F7) ..................................................................... 424 (USB EHCI—D29:F7) ..................................................................... 424 EHCI—D29:F7)............................................................................... 425 (USB EHCI—D29:F7) ..................................................................... 425 (USB EHCI—D29:F7) ..................................................................... 426 (USB EHCI—D29:F7) ..................................................................... 426 (USB EHCI—D29:F7) ..................................................................... 426 (USB EHCI—D29:F7) ..................................................................... 427 (USB EHCI—D29:F7) ..................................................................... 427 ® Intel 82801DB ICH4 Datasheet ...
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... LEG_EXT_CAP—USB EHCI Legacy Support Extended Capability 12.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / 12.1.28 SPECIAL_SMI—Intel Specific USB EHCI SMI Register 12.1.29 ACCESS_CNTL—Access Control Register 12.1.30 HS_Ref_V—USB HS Reference Voltage Register 12.2 Memory-Mapped I/O Registers....................................................................432 12.2.1 Host Controller Capability Registers ...............................................432 12 ...
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... PCISTA—Device Status Register (Modem—D31:F6) .................... 495 15.1.5 RID—Revision Identification Register (Modem—D31:F6) .............. 495 15.1.6 PI—Programming Interface Register (Modem—D31:F6) ............... 495 16 (Audio—D31:F5) ............................................................................. 472 (Audio—D31:F5) ............................................................................. 473 (Audio—D31:F5) ............................................................................. 474 (Audio—D31:F5) ............................................................................. 477 (Audio—D31:F5) ............................................................................. 477 (Audio—D31:F5) ............................................................................. 478 .......................................... 467 ....................................... 493 ® Intel 82801DB ICH4 Datasheet ...
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... Tri-State Mode .............................................................................................552 19.3 XOR Chain Mode.........................................................................................552 19.3.1 XOR Chain Testability Algorithm Example .....................................552 A Register Index B Register Bit Index ® Intel 82801DB ICH4 Datasheet (Modem—D31:F6) ..........................................................................497 (Modem—D31:F6) ..........................................................................499 (Modem—D31:F6) ..........................................................................500 (Modem—D31:F6) ..........................................................................500 ..............................................................................................511 ..............................................................................519 .......................................................................................549 .............................................................................................................551 ...
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... AC-Link Protocol.......................................................................................... 231 5-23 AC-Link Powerdown Timing ........................................................................ 238 5-24 SDIN Wake Signaling .................................................................................. 239 16-1 Intel 16-2 Intel 17-1 Clock Timing ................................................................................................ 539 17-2 Valid Delay from Rising Clock Edge ............................................................ 539 17-3 Setup and Hold Times ................................................................................. 539 17-4 Float Delay................................................................................................... 540 17-5 Pulse Width ...
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... AC ’97 Data Input and Output Timings ........................................................548 18-1 Intel 18-2 Intel 19-1 Test Mode Entry (XOR Chain Example) ......................................................551 19-2 Example XOR Chain Circuitry......................................................................552 ® Intel 82801DB ICH4 Datasheet ® ICH4 Package (Top and Side Views) ................................................549 ® ICH4 Package (Bottom View) ............................................................550 19 ...
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... Content of Interrupt Vector Byte .................................................................. 107 5-17 APIC Interrupt Mapping ............................................................................... 113 5-18 Arbitration Cycles......................................................................................... 115 5-19 APIC Message Formats............................................................................... 115 5-20 EOI Message ............................................................................................... 116 20 ® ICH4 System Power Planes................................................................. 57 ® ICH4 and System Clock Domains........................................................ 65 ® ICH4 Response to Sync Failures......................................................... 89 ® Intel 82801DB ICH4 Datasheet ...
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... DP Signal Differences..................................................................................132 5-33 Frequency Strap Behavior Based on Exit State...........................................134 5-34 Frequency Strap Bit Mapping ......................................................................134 5-35 General Power States for Systems Using Intel 5-36 State Transition Rules for Intel 5-37 System Power Plane....................................................................................137 5-38 Causes of SMI# and SCI .............................................................................138 5-39 Break Events ...
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... Input Slot 1 Bit Definitions............................................................................ 235 5-102 Output Tag Slot 0......................................................................................... 237 5-103 AC-link State during PCIRST#..................................................................... 240 6-1 PCI Devices and Functions ......................................................................... 244 6-2 Fixed I/O Ranges Decoded by Intel 6-3 Variable I/O Decode Ranges ....................................................................... 248 6-4 Memory Decode Ranges from Processor Perspective ................................ 249 7-1 LAN Controller PCI Configuration Register Address Map (LAN Controller— ...
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... XOR Chain 1................................................................................................553 19-4 XOR Chain 2................................................................................................554 19-5 XOR Chain 3................................................................................................555 19-6 XOR Chain 4-1.............................................................................................556 ® Intel 82801DB ICH4 Datasheet ® ICH4 Audio Mixer Register Configuration ..........................................479 ® ICH4 Modem Mixer Register Configuration .......................................501 ® ICH4 Ball List .....................................................................................514 23 ...
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... XOR Chain 4-2 ............................................................................................ 557 19-8 XOR Chain 6................................................................................................ 557 19-9 LONG XOR Chain ....................................................................................... 558 A-1 Intel A-2 Intel A-3 Intel 24 ® ICH4 PCI Configuration Registers ..................................................... 561 ® ICH4 Fixed I/O Registers ................................................................... 571 ® ICH4 Variable I/O Registers............................................................... 573 ® Intel 82801DB ICH4 Datasheet ...
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... Intel 82801DB ICH4 Datasheet This page is intentionally left blank 25 ...
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... Revision History Revision -001 Initial release 26 Description ® Intel 82801DB ICH4 Datasheet Date May 2002 ...
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... Chapter 4 provides a list of each clock domain associated with the ICH4 in an ICH4-based system. ® Intel 82801DB ICH4 Datasheet Specification Introduction 1 Location http://developer.intel.com/design/chipsets/ industry/lpc.htm http://developer.intel.com/ial/ scalableplatforms/audio/index.htm http://www.intel.com/labs/manage/wfm/ index.htm http://www.smbus.org/specs/ http://pcisig.com/specifications.htm http://www.t13.org http://www.usb.org http://www.acpi.info http://developer.intel.com/technology/usb/ ehcispec.htm 27 ...
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... Chapter 15 provides a detailed description of all registers that reside in the modem controller. This controller resides at Device 31, Function 6 (D31:F6). Note that this chapter of the datasheet does not include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC- link to the codec where the registers reside. 28 ® Intel 82801DB ICH4 Datasheet ...
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... Chapter 18. Package Information Chapter 18 provides drawings of the physical dimensions and characteristics of the 421-BGA package. Chapter 19. Testability Chapter 19 provides detail about the implementation of test modes provided in the ICH4. Index This document ends with indexes of registers and register bits. ® Intel 82801DB ICH4 Datasheet Introduction 29 ...
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... The LAN controller is located on Bus 1. Function Description Hub Interface to PCI Bridge PCI to LPC Bridge IDE Controller SMBus Controller AC ’97 Audio Controller AC ’97 Modem Controller USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 USB 2.0 EHCI Controller LAN Controller 2 C ® Intel 82801DB ICH4 Datasheet ...
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... Timers, Power Management, System Management, GPIO, and RTC. Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs. ® Intel 82801DB ICH4 Datasheet Introduction Section 5.15 ...
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... The ICH4 supports 6 USB 2.0 ports. All six ports are high-speed, full-speed, and low-speed capable. ICH4’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See F1 and F2) and Section 5.17, “USB EHCI Controller (D29:F7) 32 Section 5.16, “USB UHCI Controllers (D29:F0, for details. ® Intel 82801DB ICH4 Datasheet ...
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... Host Notify protocol. Hence, the host controller supports 8 command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. ® Intel 82801DB ICH4 Datasheet Introduction Section 5.2 for ...
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... Alert On LAN*. The ICH4 supports Alert On LAN and Alert On LAN 2. In response to a TCO event (intruder detect, thermal event, processor not booting) the ICH4 sends a message over the SMBus. A LAN controller can decode this SMBus message and send a message over the network to alert the network manager. 34 ® Intel 82801DB ICH4 Datasheet ...
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... AC-link. By using an audio codec, the AC-link allows for cost-effective, high-quality, integrated audio on Intel’s chipset-based platform. In addition ’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC ’97. The ICH4-integrated digital link allows several external codecs to be connected to the ICH4 ...
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... Introduction 36 This page is intentionally left blank. ® Intel 82801DB ICH4 Datasheet ...
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... When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I Input Pin O Output Pin OD Open Drain Output Pin. I/O Bi-directional Input / Output Pin. ® Intel 82801DB ICH4 Datasheet Signal Description 2 37 ...
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... Signal Description ® Figure 2-1. Intel ICH4 Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# TRDY# STOP# PERR# REQ[4:0]# REQ5# / REQB# / GPIO1 REQA# / GPIO0 GNT[4:0]# GNT5# / GNTB# / GPIO17 GNTA# / GPIO[16] PCICLK PCIRST# PLOCK# SERR# CPUSLP# FERR# IGNNE# STPCLK# A20GATE CPUPWRGD SERIRQ ...
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... Table 2-2. LAN Connect Interface Signals Name LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] LAN_RSTSYNC ® Intel 82801DB ICH4 Datasheet Type I/O Hub Interface Signals Hub Interface Strobe/ Hub Interface Strobe Second: One of two differential strobe signals used to transmit and receive data through the hub interface. ...
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... Type EEPROM Shift Clock: This signal is the serial shift clock output to the O EEPROM. EEPROM Data In: This signal transfers data from the EEPROM to the Intel I ICH4. This signal has an integrated pull-up resistor. O EEPROM Data Out: EE_DOUT transfers data from the ICH4 to the EEPROM. ...
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... PERR# REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] ® Intel 82801DB ICH4 Datasheet Type Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction output, the ICH4 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub I/O interface (main memory or AGP) ...
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... DMA but have no ISA bus. O When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors. Description ® Intel 82801DB ICH4 Datasheet ...
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... DAK# signals on the primary and secondary IDE connectors. ® ICH4 to indicate to IDE DMA slave devices that a Each is asserted by the Intel O given data transfer cycle (assertion of DIOR# or DIOW DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel ...
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... APIC Data: These bi-directional open drain signals are used to send and I/OD receive data over the APIC bus. As inputs the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK. Description Description ® Intel 82801DB ICH4 Datasheet ...
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... Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit data/address/command signals for ports 0 and 1. These ports can be routed to USB UHCI controller #1 or the USB EHCI controller. I/O NOTE: No external resistors are required on these signals. The Intel integrates 15 k pull-downs and provides an output driver impedance of 45 ...
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... The signal can also generate an SMI SCI. Thermal Trip: When low, THRMTRIP# indicates that a thermal trip from the ® processor occurred; the Intel ICH4 will immediately transition state. I The ICH4 will not wait for the processor stop grant cycle since the processor has overheated ...
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... Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. O Speed Strap: During the reset sequence, Intel corresponding bit is set in the FREQ_STRP register. CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state ...
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... Intruder Detection is not needed. System Management Link: SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that I/OD SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus Data signal. Description Description Description ® Intel 82801DB ICH4 Datasheet ...
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... RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). NOTES: ® 1. Clearing CMOS in an Intel I jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. ...
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... AC97 Serial Data Out: Serial TDM data output to the Codec(s). O NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap. See Section 2.20.1 AC97 Serial Data In 2:0: These signals are Serial TDM data inputs from the I three Codecs. Description for more details. Section 15.2.8) is set ® Intel 82801DB ICH4 Datasheet ...
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... GPIO[8] GPIO[7] GPIO[6] GPIO[5:2] GPIO[1:0] NOTE: Main power well GPIO will tolerant, except for GPIO[43:32]. Resume power well GPIO are not 5 V tolerant. ® Intel 82801DB ICH4 Datasheet Type I/O Not implemented. I/O Can be input or output. Main power well. I/O Can be input or output. Main power well. ...
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... RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an Intel by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 states ...
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... Intel 82801DB ICH4 Datasheet Usage When Sampled The signal has a weak internal pull-down. If the signal is sampled high, the Intel Rising Edge of processor speed strap pins for safe mode. Refer to PWROK processor specification for speed strapping definition. The status of this strap is readable via the SAFE_MODE bit (bit 2, D31: F0, Offset D4h) ...
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... Reference designators arbitrarily assigned. 2. 3.3 V VccSus is active when system plugged in. 3. Vbatt is voltage provided by battery. 4. VBIAS, VccRTC, RTCX1, and RTCX2 are Intel 5. VBIAS is used to bias the ICH4 internal oscillator. 6. VccRTC powers the RTC well of the ICH4. 7. RTCX1 is the input to the internal oscillator. ...
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... Driven Low after PWROK Active < 9–13 14 15–42 43– >53 ® Intel 82801DB ICH4 Datasheet (3.3 V) Diode 1 F 5VREF Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT Long XOR Reserved ...
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... Signal Description 56 This page is intentionally left blank. ® Intel 82801DB ICH4 Datasheet ...
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... This chapter describes the describes the system power planes for the ICH4. In addition, the ICH4 power planes and reset pin states for various signals are presented. 3.1 Power Planes ® Table 3-1. Intel ICH4 System Power Planes Plane Main I/O (3.3 V) Main Logic (1 ...
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... Signal Notes Integrated Series Termination Resistor Value approximately 33 (See Note) but can ® Intel 82801DB ICH4 Datasheet ...
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... Intel 82801DB ICH4 Datasheet ® Intel Tri-state. ICH4 not driving the signal high or low. ICH4 is driving the signal to a logic ‘1’ ICH4 is driving the signal to a logic ‘0’ Driven to a level that is defined by the function (will be high or low) ICH4 is driving the signal, but the value is indeterminate ...
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... High Off Off High-Z Off Off Low Off Off High Off Off High Off Off High Off Off High Off Off High-Z Off Off High-Z Off Off High-Z Off Off Low Low Low Defined Defined Defined ® Intel 82801DB ICH4 Datasheet ...
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... CPUPWRGD CPUSLP# IGNNE# INIT# INTR NMI SMI# STPCLK# SMBCLK, SMBDATA SMLINK[1:0] SPKR AC_RST# AC_SDOUT AC_SYNC ® Intel 82801DB ICH4 Datasheet ® Intel Immediately During Power after 4 PCIRST# / Plane PCIRST# 5,7 RSMRST# RSMRST# Power Management Resume I/O Low High Resume I/O Low ...
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... Resume I/O High High Main I/O High High S1 S3 S4/ Defined Off Off Defined Off Off Defined Off Off Defined Off Off Defined Off Off Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Off Off ® Intel 82801DB ICH4 Datasheet ...
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... PCICLK PDDREQ PIORDY PME# PWRBTN# PWROK RCIN# REQ[0:5]# REQ[B:A]# RI# ® Intel 82801DB ICH4 Datasheet Intel Power Well Driver During Reset Main I/O External Microcontroller Main I/O AC ’97 Codec Resume I/O AC ’97 Codec Main I/O Clock Generator Main I/O Clock Generator Main I/O ...
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... High High High High High High High High High Static Low Low High Low Low Static Low Low Driven Driven Driven Driven Driven Driven Driven Low Low Driven High High Driven Driven Driven High Low Low ® Intel 82801DB ICH4 Datasheet ...
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... For complete details of the system clocking solution refer to the system’s clock generator component specification. ® Table 4-1. Intel ICH4 and System Clock Domains Clock Frequency Domain ...
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... Figure 4-1. Conceptual System Clock Diagram Intel ICH4 32 kHz XTAL 66 66 MHz 33 MHz Clock APIC CLK Gen. 14.31818 MHz ® 48 MHz 12.288 MHz AC ’97 Codec(s) 50 MHz LAN Connect SUSCLK# (32 kHz) PCI Clocks (33 MHz) 14.31818 MHz 48 MHz ® Intel 82801DB ICH4 Datasheet ...
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... Special Cycle with the Shutdown message type. • Device Number (AD[15:11]) = 11111 • Function Number (AD[10:8]) = 111 • Register Number (AD[7:2]) = 000000 • Data = 00h • Bus number matches secondary bus number ® Intel 82801DB ICH4 Datasheet Functional Description 5 67 ...
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... PCI devices. The conceptual logic diagrams in all sources of SERR#, along with their respective enable and status bits. ICH4 error reporting logic is configured for NMI# generation. 68 Figure 5-1 and Figure 5-2 illustrate Figure 5-3 shows how the ® Intel 82801DB ICH4 Datasheet ...
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... Figure 5-2. Secondary Status Register Error Reporting Logic PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN] LPC Device Signaling an Error IOCHK# via SERIRQ D31:F0 D31_ERR_CFG Received Target Abort ® Intel 82801DB ICH4 Datasheet AND D30:F0 BRIDGE_CNT [SERR# Enable] AND D30:F0 CMD [SERR_EN] D30:F0 ERR_STS ...
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... TCO1_CNT [NMI_NOW] AND D30:F0 PD_STS [DPD] AND D30:F0 SECSTS [DPD] AND D31:F0 PCISTA [DPED] [PER] Figure 5-3 details all the parity errors that the ICH4 can detect, along To NMI# Output AND and OR Gating Logic OR NMI_EN [NMI_EN] ® Intel 82801DB ICH4 Datasheet ...
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... The ICH4 will always drive zeros on bits AD[15:11] when converting Type 1 configurations cycles to Type 0 configuration cycles on PCI. 3. Address bits [10:1] will also be passed unchanged to PCI. 4. Address bit 0 will be changed to 0. ® Intel 82801DB ICH4 Datasheet AD[31:11] During Address Phase of Type 0 Cycle on PCI 29 30 ...
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... Support of Wired for Management (WfM) Rev 2.0 • Backward compatible software with 82557, 82558 and 82559 • TCP/UDP checksum off load capabilities • Support for Intel’s Adaptive Technology 72 Section 5.1.2). This is typically Bus 1, but may be ® Intel 82801DB ICH4 Datasheet ...
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... LAN controller’s DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive Unit and Command Unit which includes transmit functions. These two units operate independently and ® Intel 82801DB ICH4 Datasheet EEPROM Interface ...
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... Mbps Ethernet LAN Connect components. The CSMA/CD unit performs all of the functions of the 802.3 protocol (e.g., frame formatting, frame stripping, collision handling, deferral to link traffic, etc.). The CSMA/CD unit can also be placed in a full-duplex mode which allows simultaneous transmission and reception of frames. 74 ® Intel 82801DB ICH4 Datasheet ...
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... TRDY# signal and provides valid data on each data access. The LAN controller allows the processor to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait- states by deasserting IRDY# when it is not ready. ® Intel 82801DB ICH4 Datasheet Functional Description 75 ...
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... The LAN controller, when detecting system error, will claim the cycle if it was the target of the transaction and continue the transaction as if the address was correct. Note: The LAN controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction. 76 ® Intel 82801DB ICH4 Datasheet ...
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... IRDY# to support zero wait-state burst cycles. The LAN controller also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by deassertion and assertion of TRDY#. ® Intel 82801DB ICH4 Datasheet Functional Description 77 ...
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... There are at least DWords of data space left in the system memory buffer. • The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b. • The MWI Enable bit in the LAN controller Configure command should is set to 1b. 78 ® Intel 82801DB ICH4 Datasheet ...
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... LAN controller also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the LAN controller during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). ® Intel 82801DB ICH4 Datasheet Functional Description 79 ...
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... MHz) for proper operation. The LAN controller supports a dynamic standby mode. In this mode, the LAN controller is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the LAN controller and is transparent to the software. 80 ® Intel 82801DB ICH4 Datasheet ...
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... The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller PCI Configuration Space, MAC configuration, and memory structure are initialized while preserving the PME# signal and its context. ® Intel 82801DB ICH4 Datasheet Functional Description 81 ...
Page 82
... The LAN controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. 82 ® Intel 82801DB ICH4 Datasheet ...
Page 83
... An EEPROM read instruction waveform is shown in Figure 5-5. Figure 5-5. 64-Word EEPROM Read Instruction Waveform EE_SHCLKK EE_CS EE_DIN EE_DOUT The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch and Dh) of the EEPROM after the deassertion of Reset. ® Intel 82801DB ICH4 Datasheet ...
Page 84
... IA, regardless of the U/L bit value. This configuration only affects the LAN controller specific IA and not multicast, multi-IA, or broadcast address filtering. The LAN controller does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit. 84 ® Intel 82801DB ICH4 Datasheet ...
Page 85
... Note: On the SMB, the send heartbeat packet command is not normally used in the D0 power state. The one exception in which it is used in the D0 state is when the system is hung. In normal operating mode, the heartbeat packets are transmitted through the ICH4 integrated LAN controller software similar to other packets. ® Intel 82801DB ICH4 Datasheet Functional Description 85 ...
Page 86
... Intel ICH4 SUS_STAT# 86 Figure 5-6. Note that the ICH4 implements all of the signals that PCI Bus PCI PCI CLK RST# LAD[3:0] LFRAME# LDRQ# (optional) LPCPD# (optional) LSMI# GPI (optional) PCI PCI PME# SERIRQ Super I/O ® Intel 82801DB ICH4 Datasheet ...
Page 87
... ICH4. Comment Single: 1 byte only Single: 1 byte only ® 1 byte only. Intel ICH4 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. (See Note 1) 1 byte only. ICH4 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. (See Note 1) ...
Page 88
... Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request 0000 deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel 0101 this encoding. It will instead use the Long Wait encoding (see next encoding below). ...
Page 89
... SYNC Time-Out There are several error cases that can occur on the LPC interface. case and the ICH4 response. ® Table 5-7. Intel ICH4 Response to Sync Failures ® Intel ICH4 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after 4 consecutive clocks. This could occur if the processor tries to access an I/O location to which no device is mapped ...
Page 90
... CYCTYPE Clock Dir & Size Clocks Clocks Clocks Start ADDR TAR Sync CYCTYPE Dir & Size Too many Syncs causes timeout Data Sync Start TAR Clocks Clocks Clock Chipset will Peripheral must drive high stop driving ® Intel 82801DB ICH4 Datasheet ...
Page 91
... LDRQ# low or tri-state it. ICH4 will shut off the LDRQ# input buffers. After driving SUS_STAT# active, the ICH4 drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. 5.3.1.12 Configuration and Intel LPC Interface Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH4 includes several decoders ...
Page 92
... DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register ® Figure 5-9. Intel ICH4 DMA Controller Each DMA channel is hardwired to the compatible settings for DMA device size: channels 3–0 are hardwired to 8-bit, count-by-bytes transfers, and channels 7– ...
Page 93
... Similarly 24-bit address is 020000h and decrements, the next address will be 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. ® Intel 82801DB ICH4 Datasheet Functional Description Section 9 ...
Page 94
... DMA service, without processor intervention, as soon as a valid DREQ is detected. 94 Current Byte/Word Count Register Bytes Words Table 5-9. 16-Bit I/O Programmed Address 8-Bit I/O Programmed Address (Ch 0–3) A0 A[16:1] A[23:17] Intel Current Address Increment/Decrement 1 1 (Ch 5–7) (Shifted) 0 A[15:0] A[23:17] ® 82801DB ICH4 Datasheet ...
Page 95
... Clear Mask Register This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7. ® Intel 82801DB ICH4 Datasheet Functional Description 95 ...
Page 96
... DMA channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1] grants DMA channel 6 to the requesting device. 96 Start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Figure 5-10. For example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0] Start Bit0 Bit1 Bit2 ® Intel 82801DB ICH4 Datasheet ...
Page 97
... The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA "fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its address representing the selected memory. ® Intel 82801DB ICH4 Datasheet Functional Description 97 ...
Page 98
... DMA cycles. BE[3:0]# 1110b 1100b I/O Read I/O Read 5-10. PCI Data Bus Connection AD[7:0] AD[15:0] Description 8-bit DMA I/O Cycle: Channels 0-3 16-bit DMA I/O Cycle: Channels 5-7 ® Intel 82801DB ICH4 Datasheet ...
Page 99
... This allows multiple DMA agents behind an I/O device to request use of the LPC interface and the I/O device does not need to self-arbitrate before sending the message. Figure 5-11. DMA Request Assertion Through LDRQ# LCLK LDRQ# ® Intel 82801DB ICH4 Datasheet Figure 5-11 Start MSB LSB ...
Page 100
... The ICH4 turns the bus around and waits for data. — The peripheral indicates data ready through SYNC and transfers the first byte. — 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. 100 ® Intel 82801DB ICH4 Datasheet ...
Page 101
... SYNC value of 1001b to the ICH4, the data will be transferred and the DMA request will remain active to the 8237 later time, the ICH4 will then come back with another START another transfer to the peripheral. ® Intel 82801DB ICH4 Datasheet CYCTYPE CHANNEL SIZE etc. combination to initiate – ...
Page 102
... To that end recommended that future devices which may appear on the LPC bus, which require higher bandwidth than 8-bit or 16-bit DMA allow with a bus mastering interface and not rely on the 8237. 102 ® Intel 82801DB ICH4 Datasheet ...
Page 103
... A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting will be affected as described in the mode definitions. The new count must follow the programmed count format. ® Intel 82801DB ICH4 Datasheet Functional Description 103 ...
Page 104
... Output goes to 1 when counter rolls over, and counter is reloaded, etc. Output is 1. Output goes to 0 when count expires for one clock time. Output is 1. Output goes to 0 when count expires for one clock time. Description ® Intel 82801DB ICH4 Datasheet ...
Page 105
... The next one or two reads, depending on whether the counter is programmed for one or two type counts, return the latched count. Subsequent reads return unlatched count. ® Intel 82801DB ICH4 Datasheet Functional Description 105 ...
Page 106
... State Machine output based on processor FERR# Internal assertion. IRQ14 from input signal (primary IDE in legacy mode Primary IDE cable only) or via SERIRQ IRQ15 from input signal (secondary IDE in legacy mode Secondary IDE Cable only) or via SERIRQ Table 5-14 Connected Pin / Function ® Intel 82801DB ICH4 Datasheet ...
Page 107
... Table 5-16. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 ® Intel 82801DB ICH4 Datasheet defines the IRR, ISR and IMR. Description Bits [7:3] ICW2[7:3] Functional Description Bits [2:0] 111 110 101 100 ...
Page 108
... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. 108 ® Intel 82801DB ICH4 Datasheet ...
Page 109
... ICW4 The final write in the sequence, ICW4, must be programmed both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.7.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • ...
Page 110
... ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read will contain bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 110 ® Intel 82801DB ICH4 Datasheet ...
Page 111
... From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. ® Intel 82801DB ICH4 Datasheet Functional Description 111 ...
Page 112
... However, active low non-ISA interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH4 receives the PIRQ input, like all of the other external sources, and routes it accordingly. 112 ® Intel 82801DB ICH4 Datasheet ...
Page 113
... IRQ # SERIRQ Yes Yes 4 Yes 5 Yes 6 Yes 7 Yes Yes 10 Yes 11 Yes 12 Yes ® Intel 82801DB ICH4 Datasheet Direct from Via PCI pin message No No Cascade from 8259 #1 No Yes No No 8254 Counter 0 No Yes No Yes No Yes No Yes No Yes No No RTC No Yes ...
Page 114
... USB UHCI controller #3, Native IDE PIRQ[D]# No USB UHCI controller #2 PIRQ[E]# Yes LAN, option for SCI, TCO PIRQ[F]# Yes Option for SCI, TCO PIRQ[G]# Yes Option for SCI, TCO PIRQ[H]# Yes USB EHCI controller, option for SCI, TCO Internal Modules ® Intel 82801DB ICH4 Datasheet ...
Page 115
... Delivery Mode bits. Table 5-19. APIC Message Formats Message Cycles EOI Short Lowest Priority Remote Read ® Intel 82801DB ICH4 Datasheet describes the arbitration cycles. Bit 0 0 Bit Normal, Bit EOI 1 1 Arbitration ID. If ICH4 samples a different value than it sent, it lost arbitration. ...
Page 116
... NOT(A1) 14 116 Bit 1 Bit EOI message ARBID 1 Arbitration ID Interrupt vector bits from redirection table NOT(V6) register NOT(V4) NOT(V2) NOT(V0) NOT(C0) Check Sum from Cycles 6– Postamble NOT(A) NOT(A) Status Cycle 0 NOT(A1) Status Cycle Idle Comments ® Intel 82801DB ICH4 Datasheet ...
Page 117
... Cycle 19 and 20 indicates the status of the message (i.e., accepted, check sum error, retry, or error). status signal combinations and their meanings for all delivery modes. ® Intel 82801DB ICH4 Datasheet Bit 0 Comments ...
Page 118
... Error 01 Error 00 Checksum Error Checksum OK: No Focus 11 Processor 10 Error Checksum OK: Focus 01 Processor 00 Checksum Error 11 Checksum OK 10 Error 01 Error 00 Checksum Error A1 Comments 1x Error 01 Accepted 00 Retry Error 01 Accepted 00 Error Error 01 End and Retry 00 Go for Low Priority Arbitration ® Intel 82801DB ICH4 Datasheet ...
Page 119
... Only the local APICs that have "free interrupt slots" will participate in the lowest priority arbitration. 2. Cycles 29 through 32 are used to break a tie in case two more processors have lowest priority. The bus arbitration IDs are used to break the tie. ® Intel 82801DB ICH4 Datasheet Bit 0 0 Normal Arbitration ...
Page 120
... Status Cycle 0. NOT(A1) Status Cycle 1. d30 d28 d26 d24 d22 d20 d18 d16 Remote register data 31-0 d14 d12 d10 d08 d06 d04 d02 d00 S Data Status valid invalid C Check Sum for data d31-d00 1 Idle Comments ® Intel 82801DB ICH4 Datasheet ...
Page 121
... PCI PIRQ[A:D], those received via SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO). The ICH4 ignores interrupt messages sent by PCI masters that attempt to use IRQ0 13. ® Intel 82801DB ICH4 Datasheet Functional Description 121 ...
Page 122
... Level-Triggered Operation In this case, the Assert Message is sent when there is an inactive-to-active edge on the interrupt. If after the EOI the interrupt is still active, then another Assert Message is sent to indicate that the interrupt is still active. 122 Section 5.8.5.5. ® Intel 82801DB ICH4 Datasheet ...
Page 123
... Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used, 2 and the redirection is limited only to those processors that are part of the logical group as based on the logical ID. 1:0 Will always be 00. ® Intel 82801DB ICH4 Datasheet Table 5-25 and Table 5-26 for the Address and Data. Description ...
Page 124
... IRQ protocol does not support the additional APIC interrupts (20–23). Note: When the IDE primary and secondary controllers are configured for native IDE mode, the only way to use the internal IRQ14 and IRQ15 connections to the Interrupt controllers is through the Serial Interrupt pin. 124 Description ® Intel 82801DB ICH4 Datasheet ...
Page 125
... The number of clocks determines the next mode: Table 5-27. Stop Frame Explanation Stop Frame Width 2 PCI clocks 3 PCI clocks ® Intel 82801DB ICH4 Datasheet Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame Continuous Mode. Only the host (ICH4) may initiate a Start Frame Functional Description ...
Page 126
... Ignored. IRQ8# can only be generated internally or on ISA Ignored. IRQ13 can only be generated from FERR not include in BM IDE interrupt logic 47 Do not include in BM IDE interrupt logic 50 Same as ISA IOCHCK# going active. 53 Drive PIRQA# 56 Drive PIRQB# 59 Drive PIRQC# 62 Drive PIRQD# Comment ® Intel 82801DB ICH4 Datasheet ...
Page 127
... To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. ® Intel 82801DB ICH4 Datasheet Functional Description Section 5.10.4 ...
Page 128
... BIOS can monitor the state of this bit and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST pulled up through a weak pull-up resistor. state when RTCRST# is asserted. 128 Table 5-29 shows which bits are set to their default ® Intel 82801DB ICH4 Datasheet ...
Page 129
... Then, once booted, the RTC_PWR_STS can be detected in the set state. Note: Clearing CMOS, using a jumper on VccRTC, must not be implemented. ® Intel 82801DB ICH4 Datasheet Default State Register ...
Page 130
... When any of these events occur, INIT# will be driven low for 16 PCI clocks, then driven high. Note: The 16-clock counter for INIT# assertion will halt while STPCLK# is active. Therefore, if INIT# is supposed to go active while STPCLK# is asserted, it will actually go active after STPCLK# goes inactive. 130 signal CC for the OH ® Intel 82801DB ICH4 Datasheet ...
Page 131
... I/O Write to F0h IGNNE# If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal IRQ13, nor will the write to F0h generate IGNNE#. ® Intel 82801DB ICH4 Datasheet Functional Description Comment transition on RCIN# must occur before the ICH4 will arm INIT generated again. ...
Page 132
... Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11). Difference Generally not used, but still supported by Intel Used for S1 State as well as preparation for entry to S3–S5 Also allows for THERM# based throttling (not via ACPI control methods). ...
Page 133
... In going to the S3, S4 states, the system will appear to pass through the S1 state, and thus STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the processors will have their power restored. ® Intel 82801DB ICH4 Datasheet Functional Description 133 ...
Page 134
... There is no processor reset frequency strap logic is used. Based on PWROK going active, the ICH4 will deassert PCIRST#, and based on the value of the S3, S4, S5, FREQ_STRAP field (D31:F0,Offset D4), the Intel or G3 values on A20M#, IGNNE#, NMI, and INTR. The ICH4 will hold these signals for 120 ns after CPURST# is deasserted by the Host controller ...
Page 135
... Table 5-35 shows the power states defined for ICH4-based platforms. The state names generally match the corresponding ACPI states. Table 5-35. General Power States for Systems Using Intel State/ Substates Full On: Processor operating. Individual devices may be shut down to save power. The different ...
Page 136
... For example, in going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate transitions and states are not listed in the table. Table 5-36. State Transition Rules for Intel Present State • ...
Page 137
... In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether interrupt shareable with a PIRQ or not; (see Section 9.1.11 ACPI Control Register for SCI sources are removed. ® Intel 82801DB ICH4 Datasheet By The SLP_S3# signal can be used to cut the processor’s power completely signal When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state ...
Page 138
... TCO SMI -Write attempted to BIOS BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event Classic USB Legacy logic Serial IRQ SMI reported 138 SCI SMI Additional Enables Yes ...
Page 139
... Table 5-39. Break Events Event Any unmasked interrupt goes active Any internal event that will cause an NMI or SMI# Any internal event that will cause INIT active Processor Pending Break Event Indication ® Intel 82801DB ICH4 Datasheet SCI SMI Additional Enables No Yes DEV[n]_TRAP_EN=1 SMB_SMI_EN No ...
Page 140
... Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and system. The Thermal Override condition will end when THRM# goes inactive. Throttling due to the THRM# signal has higher priority than the software-initiated throttling. Throttling does not occur when the system C2, even if Thermal override occurs. 140 ® Intel 82801DB ICH4 Datasheet ...
Page 141
... SLP_EN bit disables thermal throttling (since S1–S5 sleep state has higher priority). • The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power. ® Intel 82801DB ICH4 Datasheet Functional Description 141 ...
Page 142
... Upon exit from the ICH4-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in 142 for details on going to the C2 state. Comment ICH4 asserts the STPCLK# signal. It also has the option to assert the CPUSLP# signal. Table 5-41. ® Intel 82801DB ICH4 Datasheet ...
Page 143
... Table 5-42. GPI Wake Events GPI GPI[7:0] GPI[13:11], GPI[8] The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH4 are insignificant. ® Intel 82801DB ICH4 Datasheet States Can Wake From (1) – S1 ...
Page 144
... Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST# and PME_STS is cleared by RSMRST#. Table 5-43. Transitions Due to Power Failure State at Power Failure S0, S1 144 AFTERG3_EN bit Transition When Power Returns Intel ® 82801DB ICH4 Datasheet ...
Page 145
... If this bit is set, the ICH4 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared, the ICH4 stops throttling, unless the THRM# signal has been active for two seconds or if the THTL_EN bit is set (indicating that ACPI software is attempting throttling). ® Intel 82801DB ICH4 Datasheet Functional Description 145 ...
Page 146
... SCI_EN) Wake Event. Transitions to S0 state. None Unconditional transition to S5 state. seconds Comment Software will typically initiate a Sleep state. Standard wakeup No effect since no power. Not latched nor detected. No dependence on processor (e.g., Stop-Grant cycles) or any other subsystem. . ® Intel 82801DB ICH4 Datasheet ...
Page 147
... Once a reset of this type has occurred, it cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state as indicated by all of the PWROK inputs being active. ® Intel 82801DB ICH4 Datasheet Event RI_EN RI# Active ...
Page 148
... Operating systems (e.g., Microsoft Windows* 98, Windows* 2000 and Windows NT*) reprogram the system timer and, therefore, will not run into this problem. 148 ® Intel 82801DB ICH4 Datasheet ...
Page 149
... DMA Chan 0 Mode: Bits(1:0) = “00” 08h 6 4 DMA Chan 1 Mode: Bits(1:0) = “01” 5 DMA Chan 2 Mode: Bits(1:0) = “10” 6 DMA Chan 3 Mode: Bits(1:0) = “11”. ® Intel 82801DB ICH4 Datasheet Table 5-46 have read paths in ALT access mode. The access number I Data Access Addr Rds ...
Page 150
... Value Returned 000 000 Reflects bit 6 01 Restore Data Data 2 1 DMA Chan 4–7 Command 2 DMA Chan 4–7 Request 3 DMA Chan 4 Mode: Bits(1: DMA Chan 5 Mode: Bits(1: DMA Chan 6 Mode: Bits(1: DMA Chan 7 Mode: Bits(1:0) = 11. ® Intel 82801DB ICH4 Datasheet ...
Page 151
... This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal that comes from the system power supply. This saves the external AND gate found in desktop systems. ® Intel 82801DB ICH4 Datasheet Table 5-48 have write paths to them in ALT access mode. Software Register Write Value DMA Status Register for channels 0– ...
Page 152
... Based on the above principles, the following measures are taken: • During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low. 5.12.11 Clock Generators The clock generator is expected to provide the frequencies shown in ® Table 5-49. Intel ICH4 Clock Inputs Clock Frequency Domain CLK66 66 MHz ...
Page 153
... The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts. ® Intel 82801DB ICH4 Datasheet Functional Description 153 ...
Page 154
... The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. 154 Section 8.1.26) Intel ® 82801DB ICH4 Datasheet ...
Page 155
... The event messages are sent based on events occurring. The heartbeat messages is sent every seconds. When an event occurs, the ICH4 sends a new message and increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment. ® Intel 82801DB ICH4 Datasheet Section 5.13.2). ...
Page 156
... If the intervention occurs before the third timeout, then jump to rule/step11. 4. After step 3 (third timeout), if the user does a Power Button Override, the system goes state. The ICH4 continues sending heartbeats at this point. 156 ® Intel 82801DB ICH4 Datasheet ...
Page 157
... SMBus rules associated with collision detection. It delays starting a message until the bus is idle, and will detect collisions collision is detected, the ICH4 waits until the bus is idle and tries again. ® Intel 82801DB ICH4 Datasheet timeout reset is attempted (using a button that pulses PWROK low or via Functional Description ...
Page 158
... MSB (SEQ3) sent first Pre-Boot. MSB sent first Will be the same as the MESSAGE1 Register. MSB sent first. Will be the same as the MESSAGE2 Register. MSB sent first. Will be the same as the WDSTATUS Register. MSB sent first. Intel ® 82801DB ICH4 Datasheet ...
Page 159
... Input GPI[7] Only Input GPI[8] Only GPIO[9:10] N/A Input GPI[11] Only Input GPI[12] Only Input GPI[13] Only GPIO[14:15] N/A ® Intel 82801DB ICH4 Datasheet Alternate Power Tolerant (1) Function Well REQ[A]# Core 5.0 V REQ[B]# or Core 5.0 V REQ[5]# PIRQ[E:H]# Core 5.0 V Core 5.0 V ...
Page 160
... Output controlled via GP_LVL register bit 25. • TTL driver output • Not implemented • Input active status read from GP_LVL register bits [27:28] • Output controlled via GP_LVL register bits [27:28] • TTL driver output • Not implemented ® Intel 82801DB ICH4 Datasheet ...
Page 161
... Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates MB/s. • Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates 100 MB/s. ® Intel 82801DB ICH4 Datasheet Functional Description 161 ...
Page 162
... Table 5-53 Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O instructions. All other registers should be accessed using 8-bit I/O instructions. 162 specify the registers as they affect the ICH4 hardware definition. ® Intel 82801DB ICH4 Datasheet ...
Page 163
... The IDE timings for various transaction types are shown in recovery enable) of the ISA I/O Recovery Timer Register does not add wait-states to IDE data port read accesses when any of the fast timing modes are enabled. ® Intel 82801DB ICH4 Datasheet Register Function (Read) Data ...
Page 164
... Both devices attached to a connector can be programmed for bus master transfers, but only one device per connector can be active at a time. 164 Startup IORDY Sample Recovery Time Latency Point (ISP) (RCT 2–5 1–4 ® Intel 82801DB ICH4 Datasheet Shutdown Latency ...
Page 165
... If either of these conditions exist, all PCI Master non-memory read accesses to ICH4 are retried until all data in the line buffers has been transferred to memory. ® Intel 82801DB ICH4 Datasheet Byte 2 Byte 1 Byte 0 ...
Page 166
... Software issues the appropriate DMA transfer command to the disk device. 4. The bus master function is engaged by software writing the Start bit in the Command Register. The first entry in the PRD table is fetched and loaded into two registers which are not 166 ® Intel 82801DB ICH4 Datasheet ...
Page 167
... DMA transfer has started. During concurrent DMA or Ultra ATA transfers, the ICH4 IDE interface arbitrates between the primary and secondary IDE cables when a PRD expires. ® Intel 82801DB ICH4 Datasheet describes how to interpret the Interrupt and Active bits in the Status Register Functional Description ...
Page 168
... This bit combination signals an error condition. If the Error bit in the status register is set, then the controller has some problem transferring data to/from memory. Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size. ® Intel 82801DB ICH4 Datasheet ...
Page 169
... IDE device to assert DMARDY#, and then drives the first data word and STROBE signal. For read cycles, the ICH4 tri-states the DD lines, deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word and STROBE. ® Intel 82801DB ICH4 Datasheet Ultra ATA/33 Read Ultra ATA/33 Write ...
Page 170
... The ICH4 Ultra ATA/100 logic can achieve read transfer rates up to 100MB/s, and write transfer rates up to 88.9MB/s. The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100 further cable improvements are required when implementing Ultra ATA/100. 170 ® Intel 82801DB ICH4 Datasheet ...
Page 171
... IDE drive powers down, and ensures that zeros will always be returned for read cycles that occur during hot swap operation. Warning: The software should not attempt to control the outputs (either tri-state or driving low), while an IDE transfer is in progress. Unpredictable results could occur, including a system lockup. ® Intel 82801DB ICH4 Datasheet Functional Description 171 ...
Page 172
... Reserved. These bits must be written as 0. QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer (Transfer Descriptor (Queue Head). This allows the Intel type of processing on the item after it is fetched Terminate (T) ...
Page 173
... Depth/Breadth Select (VF). This bit is only valid for queued TDs and indicates to the hardware whether it should process in a depth first or breadth first fashion. When set to depth first, it informs ® the Intel ICH4 to process the next transaction in the queue rather than starting a new queue. 2 ...
Page 174
... TD. If this field is programmed with a non zero value during setup, the ICH4 decrements the count and writes it back to the TD if the transaction fails. If the counter counts from one to zero, the Intel the error that caused the transition to zero in the TD. An interrupt will be generated to Host controller Driver (HCD) if the decrement to zero was caused by Data Buffer error, Bit stuff error enabled, a CRC or Timeout error ...
Page 175
... Actual Length (ACTLEN). The Actual Length field is written by the ICH4 at the conclusion of a USB transaction to indicate the actual number of bytes that were transferred. It can be used by the 10:0 software to maintain data integrity. The value programmed in this register is encoded as n-1 (see Maximum Length field description in the TD Token). ® Intel 82801DB ICH4 Datasheet Functional Description Description 175 ...
Page 176
... Note that values from 500h to 7FEh are illegal and cause a consistency check failure. In the transmit case, the Intel fetches from host memory. In most cases, this is the number of bytes it will actually transmit. In rare cases, the ICH4 may be unable to access memory (e.g., due to excessive latency) in time to avoid underrunning the transmitter ...
Page 177
... QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer 1 is another QH Terminate (T). This bit indicates to the Intel active TDs in this queue, they are the last to be executed in this frame Pointer is valid (points TD Last QH (pointer is invalid). Table 5-63. Queue Element Link Pointer Bit Queue Element Link Pointer (QELP) ...
Page 178
... The TD/QH process continues until the millisecond allotted to the current frame expires. At this point, the ICH4 fetches the next entry from the Frame List. If the ICH4 is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. 178 ® Intel 82801DB ICH4 Datasheet ...
Page 179
... If not successful, and the error count has not been reached, leave the TD active. If the error count has been reached, mark the TD inactive 12. 11. Write the link pointer from the current TD into the element pointer field of the QH structure. If the Vf bit is set in the TD link pointer 12. Proceed to next entry. ® Intel 82801DB ICH4 Datasheet Functional Description 179 ...
Page 180
... Set USB Error Int bit Set USB Int bit TD Status Register Actions 1 1 Clear Active bit and set Stall bit 1 Clear Active bit and set Stall bit 1 1 Clear Active bit and set Stall bit Clear Active bit ® Intel 82801DB ICH4 Datasheet ...
Page 181
... Frame List Pointer Link Pointer (Horiz Link Pointer (Vert) Indicates 'NULL' Queue Head Link Pointer (Horz )=Queue Head Link Pointer field in QH DWord 0 z Link Pointer (Vert)=Queue Element Link Pointer field in QH DWord 1 ® Intel 82801DB ICH4 Datasheet Link Pointer (Horiz ...
Page 182
... Table 5-65 lists the general queue advance criteria, which are based on Host-to-Function (OUT) Error/NAK Non-NULL Retry Q Element Advance Q Table 5-65, NULL Error/NAK Advance Q Retry Q Element ® Intel 82801DB ICH4 Datasheet ...
Page 183
... QH bit in QH Table 5-66. USB Schedule List Traversal Decision Table Q QH.Q QH.T QE.Q Context 0 — — — 0 — — — 0 — — — ® Intel 82801DB ICH4 Datasheet TD QHLP TDLP QELP QE.T TD.Vf TD.Q TD.T — — — — — — ...
Page 184
... Field formats for the token, data, and handshake packets are described in the following section. The effects of NRZI coding and bit stuffing have been removed for the sake of clarity. All packets have distinct start and end of packet delimiters. 184 ® Intel 82801DB ICH4 Datasheet ...
Page 185
... Special PIDs are divided into four coding groups: token, data, handshake, and special, with the first two transmitted PID bits (PID[1:0]) indicating which group. This accounts for the distribution of PID codes. ® Intel 82801DB ICH4 Datasheet Data Sent PID 0 PID 1 PID 2 ...
Page 186
... LSB first. 186 Data Sent Bit ADDR 0 4 ADDR 1 5 ADDR 2 6 ADDR 3 Table 5-70, permits more flexible Data Sent ENDP 0 ENDP 1 ENDP 2 ENDP 3 Data Sent ADDR 4 ADDR 5 ADDR 6 Table 5-69, a ® Intel 82801DB ICH4 Datasheet ...
Page 187
... SOF PID; they can ignore the frame number and its CRC function needs to track frame number, it must comprehend both the PID and the time stamp. ® Intel 82801DB ICH4 Datasheet Width 8 bits ...
Page 188
... STALL until the condition causing the stall has been cleared through host intervention. The host is not permitted to return a STALL under any condition. 188 Width 8 bits 11 bits 5 bits Width 8 bits 0–1023 bytes 16 bits Table 5-73. There are two ® Intel 82801DB ICH4 Datasheet ...
Page 189
... USB device or by the ICH4’s CRC checker generating an error on reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not respond to a transaction phase within 19-bit times of an EOP. Either of these conditions will cause the C_ERR field of the TD to decrement. ® Intel 82801DB ICH4 Datasheet Functional Description 189 ...
Page 190
... This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is signaled to the system. 190 ® Intel 82801DB ICH4 Datasheet ...
Page 191
... The ICH4 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occur. When this error occurs, the ICH4 clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable register. ® Intel 82801DB ICH4 Datasheet Functional Description 191 ...
Page 192
... The state table for the diagram is shown in 192 Offset Bit 00h 3 Enter Global Suspend Mode (EGSM) 02h 2 Resume Detect 2 Port Enabled/Disabled 6 Resume Detect 10h & 12h 8 Low Speed Device Attached 12 Suspend Figure 5-18 Table 5-75. Description shows the Enable and Status ® Intel 82801DB ICH4 Datasheet ...
Page 193
... Figure 5-18. USB Legacy Keyboard Enable and Status Paths KBC Accesses PCI Config Read, Write USB_IRQ Clear USB_IRQ ® Intel 82801DB ICH4 Datasheet 60 READ S D Clear SMI_60_R Comb. R Decoder EN_SMI_ON_60R Same for 60W, 64R, 64W EN_PIRQD# AND AND EN_SMI_ON_IRQ Functional Description To Individual " ...
Page 194
... If Bit 7 in configuration register is set, then SMI# should be generated. Improper end of sequence. Bit 0 in the configuration register determines if cycle passed N/A IDLE through to 8042 and if SMI# generated. PSTATE goes Bit 7 in configuration register is set, then SMI# should be generated. Comment ® Intel 82801DB ICH4 Datasheet ...
Page 195
... Configure Flag and Port Status and Control bits (and any other suspend-well logic) may be in any valid state at this time. 5.17.1.2 BIOS Initialization BIOS performs a number of platform customization steps after the core well has powered up. Contact your intel field sales representative for the latest BIOS information. ® Intel 82801DB ICH4 Datasheet Table 5-66 ...
Page 196
... PCI Configuration space and BIOS- programmed parameters can not be reset. The D3-to-D0 transition must not cause wake information (suspend well lost. It also must not clear BIOS- programmed registers because BIOS may not be invoked following the D3-to- D0 transition. ® Intel 82801DB ICH4 Datasheet ...
Page 197
... Note: Once the PDE checks the length of a periodic packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the EHC switches over to run asynchronous traffic. ® Intel 82801DB ICH4 Datasheet Size (DWords) The EHC reads the entry for each microframe. The frame list is 1 not internally cached across microframes ...
Page 198
... Only the 64-bit addressing format is supported. 17 Only the 64-bit addressing format is supported. The ICH4 breaks large read requests down in to smaller aligned Up to 129 read requests based on the setting of the Read Request Max Length field. Comments Comments ® Intel 82801DB ICH4 Datasheet ...
Page 199
... DWords 14:1Fh are written. DWords 04:0Fh are written. PID Code, IOC, Buffer Pointer (Page 0), 3 and Alt. Next qTD Pointers are re-written with the original value. ® The Intel ICH4 breaks data writes down into 16 DWord aligned Up to 1297 chunks. Functional Description ...
Page 200
... If the status is Master Abort, the Received Master Abort bit in configuration space is set • If the status is Target Abort, the Received Target Abort bit in configuration space is set • If enabled (by the SERR Enable bit in the function’s configuration space), the Signaled System Error bit in configuration bit is set. 200 ® Intel 82801DB ICH4 Datasheet ...