NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 349

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

9.8.1.4
9.8.1.5
Intel
®
82801DB ICH4 Datasheet
STPCLK_DEL—Stop Clock Delay Register (PM—D31:F0)
Offset Address:
Default Value:
Power Well:
GPI_ROUT—GPI Routing Control Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
NOTE: GPIOs that are not implemented will not have the corresponding bits implemented in this register.
31:30
Bit
7:6
5:0
5:4
3:2
1:0
Bit
Reserved
STPCLK_DEL — R/W. This field selects the AC timing value for t190 (CPUSLP# inactive to
STPCLK# inactive). The default value of 0Dh yields a default of approximately 50.045
microseconds. The maximum value of 3Fh will result in a time of 245 microseconds.
NOTE: Software must program the value to a range that can be tolerated by the associated
GPI15 Route — R/W. See bits 1:0 for description.
GPI2 Route — R/W. See bits 1:0 for description.
GPI1 Route — R/W. See bits 1:0 for description.
GPI0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the GPI[n]_STS bit is
set. If the GPIO is not set to an input, this field has no effect.
If the system is in an S1
Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GP_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
processor and chipset. The Intel
00h or 01h; a minimum programming of 02h yields the minimum possible delay of 3.87 s.
A8h
0Dh
Core
B8h–BBh
0000h
No
Same pattern for GPI14 through GPI3
–
S5 state and if the GPE0_EN bit is also set, then the GPI can cause a
®
ICH4 requires that software does not program a value of
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
ACPI, Legacy
R/W
32-bit
Resume
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