NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 11

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Intel
®
82801DB ICH4 Datasheet
9.2
9.3
9.4
9.1.20 D31_ERR_STS—Device 31 Error Status Register
9.1.21 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) ......301
9.1.22 GEN_CNTL — General Control Register (LPC I/F — D31:F0) ......302
9.1.23 GEN_STA—General Status Register (LPC I/F—D31:F0) ..............304
9.1.24 BACK_CNTL—Backed Up Control Register
9.1.25 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)......305
9.1.26 COM_DEC—LPC I/F Communication Port Decode Ranges
9.1.27 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
9.1.28 SND_DEC—LPC I/F Sound Decode Ranges
9.1.29 FWH_DEC_EN1—FWH Decode Enable 1 Register
9.1.30 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
9.1.31 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ...............308
9.1.32 FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0) ..............310
9.1.33 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
9.1.34 FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0) ..............311
9.1.35 FWH_DEC_EN2—FWH Decode Enable 2 Register
9.1.36 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) ..........313
DMA I/O Registers .......................................................................................315
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10 DMA_CLMSK—DMA Clear Mask Register ....................................320
9.2.11 DMA_WRMSK—DMA Write All Mask Register ..............................320
Timer I/O Registers......................................................................................321
9.3.1
9.3.2
9.3.3
8259 Interrupt Controller (PIC) Registers ....................................................324
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
(LPC I/F—D31:F0) ..........................................................................300
(LPC I/F—D31:F0) ..........................................................................304
(LPC I/F—D31:F0) ..........................................................................305
(LPC I/F—D31:F0) ..........................................................................306
(LPC I/F—D31:F0) ..........................................................................306
(LPC I/F—D31:F0) ..........................................................................307
(LPC I/F—D31:F0) ..........................................................................308
(LPC I/F—D31:F0) ..........................................................................311
(LPC I/F—D31:F0) ..........................................................................312
DMABASE_CA—DMA Base and Current Address Registers ........316
DMABASE_CC—DMA Base and Current Count Registers............316
DMAMEM_LP—DMA Memory Low Page Registers ......................317
DMACMD—DMA Command Register ............................................317
DMASTA—DMA Status Register ....................................................318
DMA_WRSMSK—DMA Write Single Mask Register ......................318
DMACH_MODE—DMA Channel Mode Register............................319
DMA Clear Byte Pointer Register ...................................................319
DMA Master Clear Register ............................................................320
TCW—Timer Control Word Register ..............................................321
SBYTE_FMT—Interval Timer Status Byte Format Register ...........323
Counter Access Ports Register.......................................................323
ICW1—Initialization Command Word 1 Register ............................325
ICW2—Initialization Command Word 2 Register ............................326
ICW3—Master Controller Initialization Command Word 3 Register326
ICW3—Slave Controller Initialization Command Word 3 Register .327
ICW4—Initialization Command Word 4 Register ............................327
OCW1—Operational Control Word 1 (Interrupt Mask) Register .....327
OCW2—Operational Control Word 2 Register ...............................328
OCW3—Operational Control Word 3 Register ...............................328
ELCR1—Master Controller Edge/Level Triggered Register ...........329
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