NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 427

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

12.1.24
12.1.25
Intel
®
82801DB ICH4 Datasheet
FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
NOTE: This feature is used to adjust any offset from the clock source that generates the clock that drives the
PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
NOTE: This register is in the suspend power well. The intended use of this register is to establish a policy about
15:7
Bit
7:6
5:0
Bit
6:1
0
SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its
initial programmed value is system dependent based on the accuracy of hardware USB clock and is
initialized by system BIOS. This register should only be modified when the HChalted bit in the
EHCI_STS register is a 1. Changing value of this register while the host controller is operating yields
undefined results. It should not be reprogrammed by USB system software unless the default or BIOS
programmed values are incorrect, or the system is restoring the register while returning from a
suspended state.
which ports are to be used for wake events. Bit positions 1–6 in the mask correspond to a physical port
implemented on the current EHCI controller. A 1 in a bit position indicates that a device connected
below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect
or over-current events as wake-up events. This is an information-only mask register. The bits in this
register do not affect the actual operation of the EHCI host controller. The system-specific policy can be
established by BIOS initializing this register to a system-specific value. System software uses the
information in this register when enabling devices and ports for remote wake-up.
Reserved — RO. These bits are reserved for future use and should read as 00b.
Frame Length Timing Value — R/W. Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF
micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
Frame Length (# 480 MHz Clocks)
Reserved — RO.
Port Wake Up Capability Mask — R/W. Bit positions 1 through 6 correspond to a physical port
implemented on this host controller. For example, bit position 1 corresponds to port 1, bit position 2
corresponds to port 2, bit position 3 corresponds to port 3, etc.
Port Wake Implemented — R/W. A 1 in bit 0 indicates that this register is implemented to software.
59488
59504
59520
…
59984
60000
…
60480
60496
61h
20h
62
7Fh
–
63h
FLADJ Value
decimal (hex)
0 (00h)
1 (01h)
2 (02h)
31 (1Fh)
32 (20h)
62 (3Eh)
63 (3Fh)
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W
16 bits
R/W
8 bits
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