NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 489

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Intel
®
82801DB ICH4 Datasheet
23:22
21:20
19:18
Bit
25
24
17
16
15
14
13
12
10
11
9
PCM In 2 Interrupt (P2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the PCM In 2 channel status bits have been set.
Microphone 2 In Interrupt (M2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the Mic in channel interrupts status bits has been set.
Sample Capabilities
00 = Reserved
01 = 16 and 20-bit Audio supported (ICH4 value)
10 = Reserved
11 = Reserved
Multichannel Capabilities
Out.
Reserved.
MD3 — R/W. This bit is a power down semaphore for Modem. The bit exists in the suspend well and
maintains context across power states (except G3). The bit has no hardware function. It is used by
software in conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
AD3 — R/W. This bit is a power down semaphore for Audio. The bit exists in the suspend well and
maintains context across power states (except G3). The bit has no hardware function. It is used by
software in conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read completions.
0 = A codec read completes normally.
1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a
This bit is not affected by D3
Bit 3 of slot 12 — RO. Display bit 3 of the most recent slot 12.
Bit 2 of slot 12 — RO. Display bit 2 of the most recent slot 12.
Bit 1 of slot 1 2 — RO. Display bit 1 of the most recent slot 12.
AC_SDIN1 Resume Interrupt (S1RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN[1].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN0 Resume Interrupt (S0RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN[0].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN1 Codec Ready (S1CR) — RO. This bit reflects the state of the codec ready bit in
AC_SDIN[1]. Bus masters ignore the condition of the codec ready bits, so software must check this
bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
1 to the bit location.
—
RO. Indicates the capability to support more greater than 16-bit audio.
—
—
HOT
HOT
HOT
HOT
HOT
RO. Indicates the capability to support more 4 and 6 channels on PCM
RO.
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
—
RO.
Description
AC ’97 Audio Controller Registers (D31:F5)
489