ISP1161A1BMUM STEricsson, ISP1161A1BMUM Datasheet - Page 113

• Manufacturer Part Number: ISP1161A1BMUM
• Manufacturer: STEricsson

Specifications of ISP1161A1BMUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
16. Power-on reset (POR)
9397 750 13961
Product data
When V
be typically (600 ns to 1000 ns)
rising with respect to V
supply circuit.
To give a better view of the functionality,
V
the internal POR pulse will not react and will remain LOW. The internal POR starts
with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay
element will add another t
The internal POR pulse will be generated whenever V
more than 11 s.
Even if V
and on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry
by clipping the voltage above 3.3 V.
The RESET pin can be either connected to V
externally controlled (by the micro, ASIC, and so on).
Figure 50
Fig 49. Internal POR timing.
Fig 50. Clock with respect to the external POR.
CC(POR)
t0
(1) PORP = power-on reset pulse.
Stable external clock is available at A.
CC
CC
with dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is,
shows the availability of the clock with respect to the external POR.
is directly connected to the RESET pin, the internal pulse width (t
t1
t
is 5.0 V, V
PORP
Rev. 03 — 23 December 2004
EXTERNAL CLOCK
trip
trip
still remains at 2.03 V. This is because the 5 V tolerant pads
(2.03 V). The time X is decided by the external power
PORP
POR
before it drops to 0.
X, when V
t2
USB single-chip host and device controller
Figure 49
t3
CC
t
PORP
CC
is 3.3 V. X depends on how fast V
A
(using the internal POR circuit) or
shows a possible curve of
CC(POR)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t4
004aaa365
t5
drops below V
ISP1161A1
004aaa389
PORP (1)
V BAT(POR)
V trip
PORP
trip
112 of 136
11 s),
for
CC
) will
is