ISP1161A1BMUM STEricsson, ISP1161A1BMUM Datasheet - Page 89

• Manufacturer Part Number: ISP1161A1BMUM
• Manufacturer: STEricsson

Specifications of ISP1161A1BMUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13961
Product data
12.4.1 Bulk endpoints
12.4 End-Of-Transfer conditions
Table 72:
In the DACK-only mode, the ISP1161A1’s DC uses the DACK2 signal as a data
strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that
have a single address space for memory and I/O access. Such systems have no
separate MEMW and MEMR signals: the RD and WR signals are also used as
memory data strobes.
A DMA transfer to/from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConfiguration register, see
External EOT:
DMA operation and clear any remaining data in the current FIFO. For a double-
buffered endpoint the other (inactive) buffer is not affected.
When writing to an IN endpoint, an EOT will stop the DMA operation and the data
packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to
the USB host at the next IN token.
Symbol
DREQ2
DACK2
EOT
RD
WR
•
•
•
•
Fig 41. ISP1161A1’s device controller in DACK-only DMA mode.
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
DACK-only mode: pin functions
CONTROLLER
Description
DC’s DMA request
DC’s DMA
acknowledge
End-Of-Transfer
read strobe
write strobe
ISP1161A1
DEVICE
When reading from an OUT endpoint, an external EOT will stop the
Rev. 03 — 23 December 2004
D0 to D15
DREQ2
DACK2
RAM
I/O
O
I
I
I
I
USB single-chip host and device controller
DREQ
DACK
RD
WR
CONTROLLER
Function
ISP1161A1 DC requests a DMA transfer
DMA controller confirms the transfer;
also functions as data strobe
DMA controller terminates the transfer
not used
not used
DMA
HLDA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HRQ
ISP1161A1
HRQ
HLDA
CPU
Table
004aaa186
86):
88 of 136