ISP1161A1BMUM STEricsson, ISP1161A1BMUM Datasheet - Page 23

• Manufacturer Part Number: ISP1161A1BMUM
• Manufacturer: STEricsson

Specifications of ISP1161A1BMUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13961
Product data
In isochronous mode, an interrupt is issued upon each packet transaction. The
firmware must take care of timing synchronization with the host. This can be done via
the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the
DcInterruptEnable register. If a Start-Of-Frame is lost, PSOF interrupts are generated
every 1 ms. This allows the firmware to keep data transfer synchronized with the host.
After 3 missed SOF events, the DC will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF
and the PSOF interrupts and disable the interrupt for each isochronous endpoint.
Interrupt control:
The behavior of this bit is given in
Fig 21. DC interrupt logic.
Fig 22. Behavior of bit INTENA.
Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled).
DcInterruptEnable register
DcInterrupt register
SUSPND
RESUME
IEP0OUT
EP0OUT
IERESM
IESUSP
RESET
IEP0IN
EP0IN
IERST
IESOF
IEEOT
IEP14
EP14
SOF
EOT
. . .
. . .
Rev. 03 — 23 December 2004
INT2 pin
occurs. For example,
Bit INTENA in the DcMode register is a global enable/disable bit.
an interrupt event
(during this time,
SOF asserted.)
INTENA = 0
. .
.
. .
.
MGT946
A
. .
.
. .
.
Figure
SOF asserted
INTENA = 1
USB single-chip host and device controller
DcMode register
22.
INTENA
B
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
LE
SOF asserted
INTENA = 0
C
LATCH
ISP1161A1
004aaa198
INT2
22 of 136