ISP1161A1BMUM STEricsson, ISP1161A1BMUM Datasheet - Page 22

• Manufacturer Part Number: ISP1161A1BMUM
• Manufacturer: STEricsson

Specifications of ISP1161A1BMUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13961
Product data
8.6.3 DC interrupt output pin (INT2)
To re-enable the interrupt generation:
Remark: Bit InterruptPinEnable in the HcHardwareConfiguration register latches the
interrupt output. When this bit is set to logic 0, the interrupt output will remain
unchanged, regardless of any operations on the interrupt control registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal
without clearing the Hc PInterrupt register, the following procedure should be
followed:
To re-enable the interrupt generation:
The four configuration modes of DC’s interrupt output pin INT2 can also be
programmed by setting bits INTPOL and INTLVL of the DcHardwareConfiguration
register (BBH to read, BAH to write). Bit INTENA of the DcMode register (B9H to
read, B8H to write) is used to enable pin INT2.
between the interrupt events and pin INT2.
Each of the indicated USB events is logged in a status bit of the DcInterrupt register.
Corresponding bits in the DcInterruptEnable register determine whether or not an
event will generate an interrupt.
Interrupts can be masked globally by means of bit INTENA of the DcMode register
(see
The active level and signalling mode of the INT output is controlled by bits INTPOL
and INTLVL of the DcHardwareConfiguration register (see
after reset are active LOW and level mode. When pulse mode is selected, a pulse of
166 ns is generated when the OR-ed combination of all interrupt bits changes from
logic 0 to logic 1.
Bits RESET, RESUME, SP_EOT, EOT and SOF are cleared upon reading the
DcInterrupt register. The endpoint bits (EP0OUT to EP14) are cleared by reading the
associated DcEndpointStatus register.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the DcInterrupt register.
SETUP and OUT token interrupts are generated after the DC has acknowledged the
associated data packet. In bulk transfer mode, the DC will issue interrupts for every
ACK received for an OUT token or transmitted for an IN token.
1. Set all bits in the Hc PInterrupt register.
2. Set bit InterruptPinEnable to logic 1.
1. Make sure that bit InterruptPinEnable is set to logic 1.
2. Clear all bits in the Hc PInterruptEnable register.
3. Set bit InterruptPinEnable to logic 0.
1. Set all bits in the Hc PInterruptEnable register according to the HCD
2. Set bit InterruptPinEnable to logic 1.
requirements.
Table
81).
Rev. 03 — 23 December 2004
USB single-chip host and device controller
Figure 21
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
shows the relationship
Table
ISP1161A1
83). Default settings
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