MCU ARM 512K FLASH 208-TFBGA

LPC1788FET208,551

Manufacturer Part NumberLPC1788FET208,551
DescriptionMCU ARM 512K FLASH 208-TFBGA
ManufacturerNXP Semiconductors
SeriesLPC17xx
LPC1788FET208,551 datasheets
 


Specifications of LPC1788FET208,551

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed100MHzConnectivityCAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDTNumber Of I /o165
Program Memory Size512KB (512K x 8)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size96K x 8
Voltage - Supply (vcc/vdd)2.4 V ~ 3.6 VData ConvertersA/D 8x12b, D/A 1x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case208-TFBGAProcessor SeriesLPC178x
CoreARM Cortex M3Data Bus Width32 bit
Data Ram Size96 KBInterface TypeSSP, I2S, USB, JTAG, Serial, UART, I2C, SD/MMC
Maximum Clock Frequency100 MHzNumber Of Programmable I/os165
Number Of Timers4Operating Supply Voltage2.4 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Operating Temperature Range- 40 C to + 85 CSupply Current (max)100 mA
Lead Free Status / Rohs StatusLead free / RoHS CompliantOther names568-6691
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LPC178x/7x
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC
Rev. 2 — 27 May 2011
1. General description
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation.
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at
the same clock rate and other system enhancements such as modernized debug features
and a higher level of support block integration. The Cortex-M3 CPU incorporates a
3-stage pipeline and has a Harvard architecture with separate local instruction and data
buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC178x/7x is targeted to operate at
up to 120 MHz CPU frequency.
The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory controller (EMC), LCD (LPC178x only), Ethernet, USB
Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,
2
three I
C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature
Encoder Interface, four general purpose timers, two general purpose PWMs with six
outputs each and one motor control PWM, an ultra-low power RTC with separate battery
supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to
165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow
pin function compatibility with the LPC24xx and LPC23xx.
2. Features and benefits
Functional replacement for LPC23xx and 24xx family devices.
System:
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, and General Purpose DMA controller. This
interconnect provides communication with no arbitration delays unless two masters
attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Objective data sheet

LPC1788FET208,551 Summary of contents

  • Page 1

    LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 2 — 27 May 2011 1. General description The LPC178x/ ARM Cortex-M3 based microcontroller for embedded applications requiring ...

  • Page 2

    ... NXP Semiconductors  Cortex-M3 system tick timer, including an external clock input option.  Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options.  Emulation trace module supports real-time trace.  Boundary scan for simplified board testing.  ...

  • Page 3

    ... NXP Semiconductors  CAN controller with two channels.  Digital peripherals:  SD/MMC memory card interface.  165 General Purpose I/O (GPIO) pins depending on the packaging, with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M3 bit-banding ...

  • Page 4

    ... NXP Semiconductors  Clock generation:  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be used as a system clock.  ...

  • Page 5

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description LPC1788 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm LPC1788FBD208 LQFP208 LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm thin fine-pitch ball grid array package ...

  • Page 6

    ... NXP Semiconductors Table 2. LPC178x/7x ordering options All parts include two CAN channels, three SSP interfaces, three I 12-bit ADC. Type number Flash CPU (kB) SRAM (kB) LPC178x LPC1788FBD208/ 512 64 LPC1788FET208 LPC1788FET180 512 64 LPC1788FBD144 512 64 LPC1787FBD208 512 64 LPC1786FBD208 256 64 LPC1785FBD208 256 64 LPC177x LPC1778FBD208/ 512 64 LPC1778FET208 ...

  • Page 7

    ... NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE CORTEX-M3 I-code bus slave EMC slave (1) LCD slave HIGH-SPEED GPIO APB slave group 0 UART0/1 I CAN 0/1 TIMER 0/1 WINDOWED WDT PWM0/1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL EVENT RECORDER 32 kHz ...

  • Page 8

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration (LQFP208) Fig 3. Pin configuration (TFBGA208) LPC178X_7X Objective data sheet 1 LPC178x/7xFBD208 52 ball A1 index area LPC178x/ Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ...

  • Page 9

    ... NXP Semiconductors Fig 4. Pin configuration (TFBGA180) Fig 5. Pin configuration (LQFP144) 6.2 Pin description I/O pins on the LPC178x/7x are 5V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP) ...

  • Page 10

    ... NXP Semiconductors Table 3. Pin description Not all functions are available on all parts. See pins). Symbol P0[0] to P0[31] P0[0] 94 U15 M10 66 P0[1] 96 T14 N11 67 P0[2] 202 C4 D5 141 P0[3] 204 D6 A3 142 P0[4] 168 B12 A11 116 LPC178X_7X Objective data sheet Table 2 ...

  • Page 11

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[5] 166 C12 B11 115 P0[6] 164 D13 D11 113 P0[7] 162 C13 B12 112 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 12

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[8] 160 A15 C12 111 P0[9] 158 C14 A13 109 P0[10] 98 T15 L10 69 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 13

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[11] 100 R14 P12 70 P0[12 P0[13 P0[14 P0[15] 128 J16 H13 89 P0[16] 130 J14 H14 90 P0[17] 126 K17 J12 87 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 14

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[18] 124 K15 J13 86 P0[19] 122 L17 J10 85 P0[20] 120 M17 K14 83 P0[21] 118 M16 K11 82 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 15

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[22] 116 N17 L14 80 P0[23 P0[24 P0[25 P0[26 P0[27 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [6] I; I/O P0[22] — ...

  • Page 16

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[28 P0[29 P0[30 P0[31 P1[0] to P1[31] P1[0] 196 A3 B5 136 P1[1] 194 B5 A5 135 P1[2] 185 P1[3] 177 A10 A9 - LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 17

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[4] 192 A5 C6 133 P1[5] 156 A17 B13 - P1[6] 171 B11 B10 - P1[7] 153 D14 C13 - P1[8] 190 C7 B6 132 P1[9] 188 A6 D7 131 P1[10] ...

  • Page 18

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[11] 163 A14 A12 - P1[12] 157 A16 A14 - P1[13] 147 D16 D14 - P1[14] 184 A7 D8 128 P1[15] 182 A8 A8 126 P1[16] 180 D10 B8 125 P1[17] ...

  • Page 19

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[19 P1[20 P1[21 P1[22 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [3] I; I/O P1[19] — General purpose digital input/output pin. ...

  • Page 20

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[23 P1[24 P1[25] 80 T10 L7 56 P1[26] 82 R10 P8 57 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [3] I; I/O P1[23] — General purpose digital input/output pin. ...

  • Page 21

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[27] 88 T12 M9 61 P1[28] 90 T13 P10 63 P1[29] 92 U14 N10 64 P1[30 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [3] I; ...

  • Page 22

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[31 P2[0] to P2[31] P2[0] 154 B17 D12 107 P2[1] 152 E14 C14 106 P2[2] 150 D15 E11 105 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 23

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[3] 144 E16 E13 100 P2[4] 142 D17 E14 99 P2[5] 140 F16 F12 97 P2[6] 138 E17 F13 96 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 24

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[7] 136 G16 G11 95 P2[8] 134 H15 G14 93 P2[9] 132 H16 H11 92 P2[10] 110 N15 M13 76 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 25

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[11] 108 T17 M12 75 P2[12] 106 N14 N14 73 P2[13] 102 T16 M11 71 P2[14] 91 R12 - - LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 26

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[15] 99 P13 - - P2[16] 87 R11 P9 - P2[17] 95 R13 P11 - P2[18 P2[19 P2[20 P2[21] 81 U11 N8 - P2[22] 85 U12 - - P2[23 P2[24 P2[25 P2[26 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 27

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[27 P2[28 P2[29 P2[30 P2[31 P3[0] to P3[31] P3[0] 197 B4 D6 137 P3[1] 201 B3 E6 140 P3[2] 207 B1 A2 144 P3[ P3[ P3[ LPC178X_7X Objective data sheet Table 2 ...

  • Page 28

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[ P3[ P3[8] 191 P3[9] 199 P3[10] 205 P3[11] 208 P3[12 P3[13 P3[14 P3[15 P3[16] 137 F17 - - P3[17] 143 F15 - - P3[18] 151 C15 - - LPC178X_7X Objective data sheet ...

  • Page 29

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[19] 161 B14 - - P3[20] 167 A13 - - P3[21] 175 C10 - - P3[22] 195 P3[23 P3[24 P3[25 P3[26 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 30

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[27] 203 P3[28 P3[29 P3[30 P3[31 P4[0] to P4[31] P4[ P4[1] 79 U10 M7 55 P4[2] 83 T11 M8 58 P4[3] 97 U16 K9 68 P4[4] 103 R15 P13 72 P4[5] 107 R16 H10 74 ...

  • Page 31

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[6] 113 M14 K10 78 P4[7] 121 L16 K12 84 P4[8]/ 127 J17 J11 88 P4[9] 131 H17 H12 91 P4[10] 135 G17 G12 94 P4[11] 145 F14 F11 101 ...

  • Page 32

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[21] 115 M15 - - P4[22] 123 K14 - - P4[23] 129 J15 - - P4[24] 183 B8 C8 127 P4[25] 179 B9 D9 124 P4[26] 119 L15 K13 - P4[27] 139 G15 F14 ...

  • Page 33

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[29] 176 B10 B9 122 P4[30] 187 B7 C7 130 P4[31] 193 A4 E7 134 P5[0] to P5[4] P5[ P5[ P5[2] 117 L14 L12 81 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

  • Page 34

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P5[3] 141 G14 G10 98 P5[4] 206 C3 C4 143 JTAG_TDO (SWO) JTAG_TDI JTAG_TMS (SWDIO) JTAG_TRST JTAG_TCK (SWDCLK) RESET RSTOUT RTC_ALARM RTCX1 RTCX2 USB_D VBAT 38 M3 ...

  • Page 35

    ... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol V 26, H4, G1, 18, DD(REG)(3V3) 86, P11, N9, 60, 174 D11 E9 121 DDA V 15, G3, E2, 41, DD(3V3) 60, P6, L4, 62, 71, P8, K8, 77, 89, U13, L11, 102, 112, P17, J14, 114, 125, ...

  • Page 36

    ... NXP Semiconductors [ Input Output Ground Supply. [ tolerant pad providing digital I/O functions with TTL levels and hysteresis. [4] <tbd> [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled. ...

  • Page 37

    ... NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol 9 P1[ P0[ P2[4] Row E 1 P0[26 P2[6] Row F 1 P0[25 P3[16] Row G 1 P3[ P4[10] Row H 1 P0[23 P4[9] Row J 1 P3[ P4[8] Row K 1 VREFP ...

  • Page 38

    ... NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol P0[19] Row M 1 P3[15 P0[20] Row N 1 RTC_ALARM P0[22] Row P 1 P1[31 P2[24 P1[23 P2[15 DD(3V3) Row R 1 P0[12 P3[24 P2[17 P4[20] ...

  • Page 39

    ... NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row A 5 P1[ P1[ P0[9] 14 Row B 1 JTAG_TDO_SWO 2 5 P1[ P4[29 P1[5] 14 Row C 1 P3[13 DD(3V3) 9 P1[17 P1[7] 14 Row D 1 P0[26 P0[ P4[25 Row E 1 P0[24] ...

  • Page 40

    ... NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row J 1 RESET 2 5 P0[13 P0[18] 14 Row K 1 VBAT 2 5 P0[29 P4[ P4[26] 14 Row L 1 P2[29 P1[18 Row M 1 P0[28 P0[14 P1[27 P2[10] ...

  • Page 41

    ... NXP Semiconductors The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption ...

  • Page 42

    ... NXP Semiconductors The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place ...

  • Page 43

    APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved (1) 16 SD/MMC 0x400C 0000 (1) 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 reserved 13 0x400B ...

  • Page 44

    ... NXP Semiconductors 7.8 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.8.1 Features • Controls system exceptions and peripheral interrupts. • ...

  • Page 45

    ... NXP Semiconductors Table 7. External memory controller pin configuration Part Data bus pins Address bus LPC1788FBD208 EMC_D[31:0] LPC1788FET208 EMC_D[31:0] LPC1788FET180 EMC_D[15:0] LPC1788FBD144 EMC_D[7:0] LPC1787FBD208 EMC_D[31:0] LPC1786FBD208 EMC_D[31:0] LPC1785FBD208 EMC_D[31:0] LPC1778FBD208 EMC_D[31:0] LPC1778FET208 EMC_D[31:0] LPC1778FET180 EMC_D[15:0] LPC1778FBD144 EMC_D[7:0] LPC1777FBD208 EMC_D[31:0] LPC1776FBD208 EMC_D[31:0] LPC1776FET180 ...

  • Page 46

    ... NXP Semiconductors The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral ...

  • Page 47

    ... NXP Semiconductors 7.11.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • ...

  • Page 48

    ... NXP Semiconductors • Accept any size of data width per write 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle) 7.13 LCD controller Remark: The LCD controller is available on parts LPC1788/87/86/85. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024  ...

  • Page 49

    ... NXP Semiconductors 7.14 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...

  • Page 50

    ... NXP Semiconductors – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.15 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85 and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774. ...

  • Page 51

    ... NXP Semiconductors • Supports per-port power switching 7.15.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I interface to implement OTG dual-role device functionality ...

  • Page 52

    ... NXP Semiconductors • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. ...

  • Page 53

    ... NXP Semiconductors 7.19.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support 7.20 UARTs Remark: USART4 is not available on part LPC1774FBD144. The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data ...

  • Page 54

    ... NXP Semiconductors during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. ...

  • Page 55

    ... NXP Semiconductors 2 7.23 I S-bus serial I/O controllers The LPC178x/7x contain one I communication interface for digital audio applications. 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave ...

  • Page 56

    ... NXP Semiconductors • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.25 General purpose 32-bit timers/external event counters The LPC178x/7x include four 32-bit timer/counters ...

  • Page 57

    ... NXP Semiconductors Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs ...

  • Page 58

    ... NXP Semiconductors PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2 Table 8 ...

  • Page 59

    ... NXP Semiconductors 7.30 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.30.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • ...

  • Page 60

    ... NXP Semiconductors • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. ...

  • Page 61

    ... NXP Semiconductors IRC oscillator main oscillator Fig 7. LPC178x/7x clock generation block diagram 7.33.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range ...

  • Page 62

    ... NXP Semiconductors 7.33.1.3 RTC oscillator The RTC oscillator provides clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.33.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled ...

  • Page 63

    ... NXP Semiconductors 7.33.3 Wake-up timer The LPC178x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

  • Page 64

    ... NXP Semiconductors The DMA controller can continue to work in Sleep mode, and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. ...

  • Page 65

    ... NXP Semiconductors 7.33.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator ...

  • Page 66

    ... NXP Semiconductors The second option uses two power supplies; a 3.3 V supply for the I/O pads (V a dedicated 3.3 V supply for the CPU (V powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. ...

  • Page 67

    ... NXP Semiconductors Section 7.33.3), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values ...

  • Page 68

    ... NXP Semiconductors 7.34.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.34.5 AHB multilayer matrix The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM ...

  • Page 69

    ... NXP Semiconductors 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREFP ...

  • Page 70

    ... NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • ambient temperature (C), amb • R th(j-a) • sum of internal and I/O power dissipation D The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications ...

  • Page 71

    ... NXP Semiconductors 10. Static characteristics Table 11. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

  • Page 72

    ... NXP Semiconductors Table 11. Static characteristics …continued    +85 C, unless otherwise specified. amb Symbol Parameter I ADC supply current DD(ADC) I ADC input current I(ADC) Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...

  • Page 73

    ... NXP Semiconductors Table 11. Static characteristics …continued    +85 C, unless otherwise specified. amb Symbol Parameter V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range ...

  • Page 74

    ... NXP Semiconductors [9] All internal pull-ups disabled. All pins configured as output and driven LOW C. [10 3 DDA amb = 25 C. [11 3 i(VREFP) amb [12] Including voltage on outputs in 3-state mode. [13] V supply voltages must be present. DD(3V3) [14] 3-state outputs go into 3-state mode in Deep power-down mode. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. ...

  • Page 75

    ... NXP Semiconductors X (X) Conditions: V Fig 10. Power-down mode: Regulator supply current I X (X) Conditions: V Fig 11. Deep power-down mode: Battery supply current I LPC178X_7X Objective data sheet <tbd> 3.3 V; BOD disabled. DD(Reg)(3V3 <tbd> 3 floating; RTC not running. BAT DD(Reg)(3V3) All information provided in this document is subject to legal disclaimers. ...

  • Page 76

    ... NXP Semiconductors 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample  ...

  • Page 77

    ... NXP Semiconductors Table 12.  amb Peripheral EMC RTC USB + PLL1 Ethernet LPC178X_7X Objective data sheet Power consumption for individual analog and digital blocks <tbd> V. PCLK = CCLK/4. DD(REG)(3V3) Conditions PCENET bit set the PCONP register All information provided in this document is subject to legal disclaimers. ...

  • Page 78

    ... NXP Semiconductors 10.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 Conditions: V Fig 12. Typical HIGH-level output voltage (mA) 10 Conditions: V Fig 13. Typical LOW-level output current I LPC178X_7X Objective data sheet °C 25 °C −40 ° 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3 0 3.3 V; standard port pins. ...

  • Page 79

    ... NXP Semiconductors I (μA) Conditions: V Fig 14. Typical pull-up current (μ −10 Conditions: V Fig 15. Typical pull-down current I LPC178X_7X Objective data sheet +10 pu −10 − °C 25 °C −40 °C −50 − 3.3 V; standard port pins. DD(REG)(3V3) DD(3V3) versus input voltage °C 25 °C −40 °C ...

  • Page 80

    ... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 13.  amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 14.  amb Symbol ...

  • Page 81

    ... NXP Semiconductors 11.2 External memory interface Table 15. Dynamic characteristics: Static external memory interface    pF amb [1] Symbol Parameter T clock cycle time cy(clk) [2] Read cycle parameters t CS LOW to address valid CSLAV time t CS LOW to OE LOW time CSLOEL t CS LOW to BLS LOW time ...

  • Page 82

    ... NXP Semiconductors Table 15. Dynamic characteristics: Static external memory interface    pF amb [1] Symbol Parameter t BLS LOW to BLS HIGH time WR BLSLBLSH t BLS HIGH to end of write BLSHEOW time t BLS HIGH to data invalid BLSHDNV time [1] Parameters are shown [2] Parameters specified for DD(IO) [3] Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1). ...

  • Page 83

    ... NXP Semiconductors BLSx WE D Fig 17. External static memory read/write access (PB = BLSx Fig 18. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits    pF amb Values guaranteed by design. Symbol Parameter Common to read and write cycles ...

  • Page 84

    ... NXP Semiconductors Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits    pF amb Values guaranteed by design. Symbol Parameter t write hold time h(W) t output enable valid delay time d(GV) t output enable hold time h(G) t address valid delay time ...

  • Page 85

    ... NXP Semiconductors [1] The data input set-up time has to be selected with the following margin: + delay time of feedback clock  sdram access time  board delay time  su(D) [2] The data input hold time has to be selected with the following margin: + sdram access time - board delay time - delay time of feedback clock  0. ...

  • Page 86

    ... NXP Semiconductors 11.3 External clock Table 19.  amb Symbol f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 20. External clock timing (with an amplitude of at least V 11 ...

  • Page 87

    ... NXP Semiconductors X (X) Conditions: Frequency values are typical values. 12 MHz  accuracy is guaranteed for 2.7 V  fall outside the 12 MHz  accuracy specification for voltages below 2.7 V. Fig 21. Internal RC oscillator frequency versus temperature 11.5 I/O pins Table 21.  amb Symbol [1] Applies to standard port pins and RESET pin. ...

  • Page 88

    ... NXP Semiconductors Table 22.  amb Symbol T cy(clk v(Q) t h(Q) = (SSPCLKDIV  SCR)  CPSDVSR [1] T cy(clk function of the main clock frequency f cy(clk) SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). = 40  C; V ...

  • Page 89

    ... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP slave timing in SPI mode 2 11.7 I C-bus Table 23.  amb Symbol f SCL LOW t HIGH LPC178X_7X Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t DS MOSI DATA VALID t v(Q) MISO DATA VALID ...

  • Page 90

    ... NXP Semiconductors Table 23.  amb Symbol t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. [ the data hold time that is measured from the falling edge of SCL; applies to data in transmission HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL ...

  • Page 91

    ... NXP Semiconductors 2 11.8 I S-bus interface Table 24.  amb Symbol common to input and output output t v(Q) input t su(D) t h(D) [1] CCLK = 100 MHz; peripheral clock to the I 1600 ns, corresponds to the SCK signal in the I I2S_TX_SCK I2S_TX_SDA I2S_TX_WS Fig 25. I LPC178X_7X Objective data sheet 2 Dynamic characteristics: I S-bus interface pins  ...

  • Page 92

    ... NXP Semiconductors I2S_RX_SCK I2S_RX_SDA I2S_RX_WS Fig 26. I 11.9 USB Table 25. Dynamic characteristics of USB pins (full-speed)  pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP ...

  • Page 93

    ... NXP Semiconductors t PERIOD crossover point differential data lines differential data to n × t Fig 27. Differential data-to-EOP transition skew and EOP width 11.10 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. Table 26.  amb Symbol Parameter RMII mode f clock frequency clk ...

  • Page 94

    ... NXP Semiconductors Fig 28. Ethernet timing 11.11 LCD Remark: The LCD controller is available on parts LPC1788/87/86/85. Table 27. Values listed describe design constraints. Symbol T cy(clk) X (X) Fig 29. LCD timing 11.12 SD/MMC Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts LPC1778/77/76. LPC178X_7X Objective data sheet ...

  • Page 95

    ... NXP Semiconductors Table 28.  amb Symbol f clk t su(D) t h(D) t d(QV) t h(Q) Fig 30. SD/MMC timing 12. ADC electrical characteristics Table DDA Symbol vsi 12-bit resolution; 400 kSamples/sec L(adj clk(ADC) LPC178X_7X Objective data sheet Dynamic characteristics: SD/MMC   3 3.6 V. Values guaranteed by design. ...

  • Page 96

    ... NXP Semiconductors Table DDA Symbol f c(ADC) 8-bit resolution L(adj clk(ADC) f c(ADC) [1] Conditions: V [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (E See Figure [4] The integral non-linearity (E the ideal transfer curve after appropriate adjustment of gain and offset errors. See ...

  • Page 97

    ... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 31. 12-bit ADC characteristics LPC178X_7X Objective data sheet ...

  • Page 98

    ... NXP Semiconductors The values of resistor components R process-dependent. Fig 32. ADC interface to pins ADC0_IN[n] Table 30. Component 13. DAC electrical characteristics Table DDA Symbol L(adj LPC178X_7X Objective data sheet LPC17xx kΩ - 5.2 kΩ 2.2 pF ADC COMPARATOR BLOCK C1 750 and R i1 ADC interface components Range Description 2 k ...

  • Page 99

    ... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774. LPC17xx Fig 33. USB interface on a self-powered device LPC17xx Fig 34. USB interface on a bus-powered device LPC178X_7X ...

  • Page 100

    ... NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 35. USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 36. USB host port configuration LPC178X_7X Objective data sheet V DD RESET_N ADR/PSW OE_N/INT_N V DD SPEED ISP1302 SUSPEND ...

  • Page 101

    ... NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D− V BUS Fig 37. USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

  • Page 102

    ... NXP Semiconductors Fig 39. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 32. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 33. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 14.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...

  • Page 103

    ... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 14.4 Standard I/O pin configuration Figure 40 • Digital output driver: Open-drain mode enabled/disabled • ...

  • Page 104

    ... NXP Semiconductors 14.5 Reset pin configuration reset Fig 41. Reset pin configuration LPC178X_7X Objective data sheet GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ESD PIN ESD V SS 002aaf274 © NXP B.V. 2011. All rights reserved. ...

  • Page 105

    ... NXP Semiconductors 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 106

    ... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 15.1 mm 1.2 0.3 0.6 14.9 0.4 OUTLINE VERSION IEC SOT950-1 Fig 43. TFBGA208 package ...

  • Page 107

    ... NXP Semiconductors TFBGA180: thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions UNIT max. 0.35 0.85 0.5 12.2 mm 1.2 0.25 0.75 0.4 11.8 OUTLINE VERSION IEC SOT570-2 Fig 44. TFBGA180 package ...

  • Page 108

    ... NXP Semiconductors LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 109

    ... NXP Semiconductors 16. Soldering Footprint information for reflow soldering of LQFP208 package solder land occupied area DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 46. Reflow soldering of the LQFP208 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...

  • Page 110

    ... NXP Semiconductors Footprint information for reflow soldering of TFBGA180 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.400 0.400 0.550 12.575 12.575 Fig 47. Reflow soldering of the TFBGA180 package LPC178X_7X Objective data sheet ...

  • Page 111

    ... NXP Semiconductors Footprint information for reflow soldering of LQFP144 package solder land occupied area DIMENSIONS 0.500 0.560 23.300 23.300 20.300 20.300 Fig 48. Reflow soldering of the LQFP144 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...

  • Page 112

    ... NXP Semiconductors 17. Abbreviations Table 34. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO GPS HVAC IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLC PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB ...

  • Page 113

    ... NXP Semiconductors 18. Revision history Table 35. Revision history Document ID Release date LPC178X_7X v.2 20110527 • Modifications: Symbol names in • Reserved functions added in • Added function LCD_VD[5] to pin P0[10]. • Added function LCD_VD[10] to pin P0[11]. • Added function LCD_VD[13] to pin P0[19]. • Added function LCD_VD[14] to pin P0[20]. ...

  • Page 114

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 115

    ... For sales office addresses, please send an email to: LPC178X_7X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

  • Page 116

    ... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 40 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 40 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 41 7.3 On-chip flash program memory . . . . . . . . . . . 41 7.4 EEPROM ...

  • Page 117

    ... NXP Semiconductors 7.35 Emulation and debugging . . . . . . . . . . . . . . . . 68 8 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . 70 9.1 Thermal characteristics Static characteristics 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 74 10.2 Peripheral power consumption . . . . . . . . . . . . 76 10.3 Electrical pin characteristics . . . . . . . . . . . . . . 78 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 80 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2 External memory interface . . . . . . . . . . . . . . . 81 11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.4 Internal oscillators ...