AD9514BCPZ Analog Devices Inc, AD9514BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD9514BCPZ
• Description: IC CLOCK DIST 3OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9514BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.6GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 1.6GHz
• No. Of Multipliers / Dividers: 3
• No. Of Amplifiers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9514/PCBZ - BOARD EVAL CLOCK 3CH AD9514
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9514
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
SYNCB
VREF
S0 TO S10
POWER
Table 7.
Parameter
POWER-ON SYNCHRONIZATION
POWER DISSIPATION
POWER DELTA
1
This is the rise time of the V
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
V
Divider (Divide = 2 to Divide = 1)
LVPECL Output
LVDS Output
CMOS Output (Static)
CMOS Output (@ 62.5 MHz)
CMOS Output (@ 125 MHz)
Delay Block
Logic High
Logic Low
Capacitance
Output Voltage
Levels
S
Transit Time from 2.2 V to 3.1 V
0
1/3
2/3
1
S
supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the V
Min
2.7
0.62 V
0.2 V
0.55 V
0.9 V
1
S
S
S
S
Min
295
380
410
110
15
65
20
30
80
30
Typ
2
Typ
405
490
525
110
150
30
90
50
40
45
Max
550
635
680
125
140
190
Max
0.40
0.76 V
0.1 V
0.45 V
0.8 V
35
45
85
50
65
S
S
S
S
Unit
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
ms
Rev. 0 | Page 10 of 28
Unit
V
V
pF
V
V
V
V
V
Test Conditions/Comments
See Figure 24.
All outputs on. 2 LVPECL (divide = 2), 1 LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
All outputs on. 2 LVPECL (divide = 2), 1 CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
All outputs on. 2 LVPECL, 1 CMOS (divide = 2); At 125 MHz out (5 pF load).
For each divider. No clock.
For each output. No clock.
No clock.
No clock.
Single-ended. At 62.5 MHz out with 5 pF load.
Single-ended. At 125 MHz out with 5 pF load.
Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
Test Conditions/Comments
Minimum − maximum from 0 mA to 1 mA load
S
to