AD9514BCPZ Analog Devices Inc, AD9514BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9514BCPZ
• Description: IC CLOCK DIST 3OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9514BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.6GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 1.6GHz
• No. Of Multipliers / Dividers: 3
• No. Of Amplifiers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9514/PCBZ - BOARD EVAL CLOCK 3CH AD9514
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9514
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVPECL
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL
LVDS
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS
CMOS
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS
LVPECL-TO-LVDS OUT
LVPECL-TO-CMOS OUT
DELAY ADJUST (OUT2; LVDS and CMOS)
Output Rise Time, t
Output Fall Time, t
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUT0 to OUT1 on Same Part, t
Both LVPECL Outputs Across Multiple Parts, t
Same LVPECL Output Across Multiple Parts, t
Output Rise Time, t
Output Fall Time, t
Divide = 1
Divide = 2 − 32
Variation with Temperature
LVDS Output Across Multiple Parts, t
Output Rise Time, t
Output Fall Time, t
Divide = 1
Divide = 2 − 32
Variation with Temperature
CMOS Output Across Multiple Parts, t
Output Delay, t
Output Delay, t
S0 = 1/3
S0 = 2/3
Zero Scale Delay Time
Full Scale Time Delay
Zero Scale Delay Time
Full Scale Time Delay
Zero Scale Variation with Temperature
Full Scale Variation with Temperature
Zero Scale Variation with Temperature
Full Scale Variation with Temperature
SKV_C
SKV_C
FP
FL
FC
RP
RL
RC
PECL
LVDS
CMOS
3
3
3
3
, CLK-TO-LVPECL OUT
, CLK-TO-LVDS OUT
, CLK-TO-CMOS OUT
SKP
1
SKV_AB
SKC_AB
2
2
SKP_AB
SKP_AB
2
2
Min
355
395
−50
1.00
1.05
1.10
1.15
560
700
Rev. 0 | Page 4 of 28
Typ
60
60
480
530
0.5
0
200
210
1.25
1.30
0.9
650
650
1.45
1.50
1
790
970
0.34
0.20
1.7
−0.38
0.45
0.31
5.9
−1.3
Max
100
100
635
710
+55
125
125
350
350
1.55
1.60
230
865
990
1.75
1.80
300
950
1150
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ns
ns
ps/°C
ps
ps
ps
ns
ns
ps/°C
ps
ps
ps
ns
ps/°C
ns
ps/°C
ns
ps/°C
ns
ps/°C
Test Conditions/Comments
Termination = 50 Ω to V
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential, 3.5 mA
20% to 80%, measured differentially
80% to 20%, measured differentially
Optional delay off
Optional delay off
B outputs are inverted; termination = open
20% to 80%; C
80% to 20%; C
Optional delay off
Optional delay off
LOAD
LOAD
= 3 pF single-ended
= 3 pF single-ended
S
− 2 V