AD9514BCPZ Analog Devices Inc, AD9514BCPZ Datasheet - Page 13

IC CLOCK DIST 3OUT PLL 32LFCSP

AD9514BCPZ

Manufacturer Part Number
AD9514BCPZ
Description
IC CLOCK DIST 3OUT PLL 32LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Buffer (Distribution), Dividerr
Datasheet

Specifications of AD9514BCPZ

Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
Yes/Yes
Input
Differential
Output
CMOS, LVDS, LVPECL
Frequency - Max
1.6GHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Frequency-max
1.6GHz
No. Of Multipliers / Dividers
3
No. Of Amplifiers
4
Supply Voltage Range
3.135V To 3.465V
Slew Rate
1V/ns
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9514/PCBZ - BOARD EVAL CLOCK 3CH AD9514
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9514BCPZ
Manufacturer:
ADI
Quantity:
526
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No.
1, 4 ,17, 20, 21,
24, 26, 29, 30
2
3
5
6
7 to 16, 25
18
19
22
23
27
28
31, Exposed Paddle
32
SYNCB
CLKB
VREF
CLK
S10
VS
VS
S9
1
2
4
5
6
7
8
3
Figure 6. 32-Lead LFCSP Pin Configuration
Mnemonic
VS
CLK
CLKB
SYNCB
VREF
S10 to S0
OUT2B
OUT2
OUT1B
OUT1
OUT0B
OUT0
GND
RSET
(Not to Scale)
AD9514
TOP VIEW
Description
Power Supply (3.3 V).
Clock Input.
Complementary Clock Input.
Used to Synchronize Outputs; Do Not Let Float.
Provides 2/3 V
Setup Select Pins. These are 4-state logic. The logic levels are V
The VREF pin provides 2/3 V
that logic level should be left no connection (NC).
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Ground. The exposed paddle on the back of the chip is also GND.
Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
24 VS
23 OUT1
22 OUT1B
21 VS
20 VS
19 OUT2
18 OUT2B
17 VS
S
for Use as One of the Four Logic Levels on S0 to S10.
Rev. 0 | Page 13 of 28
S
. Each pin is internally biased to 1/3 V
24
17
16
THERMAL CONNECTION
IS AN ELECTRICAL AND
25
THE EXPOSED PADDLE
Figure 7. Exposed Paddle
(BOTTOM VIEW)
EXPOSED PAD
S
, GND, 1/3 V
GND
S
so that a pin requiring
S
32
, and 2/3 V
9
1
8
S
.
AD9514

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