IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 118

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

PRIORITY_TABLE2_STS - Priority Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration
Programming Information
IDT82V3280
Address: 4FH
Type: Read
Default Value: 00000000
Address: 50H
Type: Read / Write
Default Value: XXXX0000
ST_PRIORITY_
THIRD_HIGHE
VALIDATED3
7 - 4
3 - 0
7 - 4
3 - 0
Bit
Bit
7
7
-
T0_INPUT_SEL[3:0]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
ST_PRIORITY_
THIRD_HIGHE
VALIDATED2
Name
-
6
-
6
Reserved.
This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’.
0000: Automatic selection. (default)
0001: Forced selection - IN1 is selected.
0010: Forced selection - IN2 is selected.
......
1101: Forced selection - IN13 is selected.
1110: Forced selection - IN14 is selected.
1111: Reserved.
Name
ST_PRIORITY_
THIRD_HIGHE
VALIDATED1
5
-
5
ST_PRIORITY_
THIRD_HIGHE
VALIDATED0
4
-
These bits indicate a qualified input clock with the third highest priority.
0000: No input clock is qualified. (default)
0001: IN1.
0010: IN2.
......
1101: IN13.
1110: IN14.
1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b7-0,
4CH) or INn (b5-0, 4DH) bit is ‘0’.
These bits indicate a qualified input clock with the second highest priority.
0000: No input clock is qualified. (default)
0001: IN1.
0010: IN2.
......
1101: IN13.
1110: IN14.
1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b7-0,
4CH) or INn (b5-0, 4DH) bit is ‘0’.
4
T0_INPUT_SEL3
118
SECOND_HIGH
EST_PRIORITY
_VALIDATED3
3
3
Description
T0_INPUT_SEL2
SECOND_HIGH
EST_PRIORITY
_VALIDATED2
2
2
Description
T0_INPUT_SEL1
SECOND_HIGH
EST_PRIORITY
_VALIDATED1
1
1
December 9, 2008
T0_INPUT_SEL0
SECOND_HIGH
EST_PRIORITY
_VALIDATED0
0
0
WAN PLL