IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 60

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

Table 42: Register List and Map (Continued)
Programming Information
IDT82V3280
Address
(Hex)
0B
7E
0C
0D
0E
1A
1B
1C
1D
1E
13
7F
0F
10
12
14
15
16
17
18
19
11
MON_SW_PBO_CNFG - Frequency
Monitor, Input Clock Selection & PBO
Control
MS_SL_CTRL_CNFG - Master Slave
Control
PROTECTION_CNFG - Register Pro-
tection Mode Configuration
MPU_SEL_CNFG - Microprocessor
Interface Mode Configuration
INTERRUPT_CNFG - Interrupt Config-
uration
INTERRUPTS1_STS - Interrupt Status
1
INTERRUPTS2_STS - Interrupt Status
2
INTERRUPTS3_STS - Interrupt Status
3
INTERRUPTS1_ENABLE_CNFG
Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG
Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG
Interrupt Control 3
IN1_CNFG - Input Clock 1 Configura-
tion
IN2_CNFG - Input Clock 2 Configura-
tion
IN3_CNFG - Input Clock 3 Configura-
tion
IN4_CNFG - Input Clock 4 Configura-
tion
IN5_IN6_HF_DIV_CNFG - Input Clock
5 & 6 High Frequency Divider Configu-
ration
IN5_CNFG - Input Clock 5 Configura-
tion
IN6_CNFG - Input Clock 6 Configura-
tion
IN7_CNFG - Input Clock 7 Configura-
tion
IN8_CNFG - Input Clock 8 Configura-
tion
IN9_CNFG - Input Clock 9 Configura-
tion
IN10_CNFG - Input Clock 10 Configu-
ration
Register Name
-
-
-
ATING_MO
ATING_MO
FREQ_MO
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
T0_OPER
EX_SYNC
T0_OPER
EX_SYNC
Input Clock Frequency & Priority Configuration Registers
_ALARM
_ALARM
N_CLK
Bit 7
DE
DE
IV
IV
IV
IV
IV
IV
IV
IV
-
-
-
-
-
IN6_DIV[1:0]
400HZ_SE
400HZ_SE
T0_MAIN_
T0_MAIN_
G_TO_TD
REF_FAIL
REF_FAIL
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
LOS_FLA
T4_STS
T4_STS
Bit 6
ED
ED
O
L
L
-
-
-
Interrupt Registers
ULTR_FAS
T_SW
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
Bit 5
60
-
-
-
-
-
-
PROTECTION_DATA[7:0]
INPUT_TO
INPUT_TO
EXT_SW
Bit 4
_T4
_T4
-
-
-
-
IN[8:1]
IN[8:1]
PBO_FRE
AMI2_VIO
AMI2_VIO
Bit 3
Z
L
L
-
-
-
-
IN[14:9]
IN[14:9]
AMI2_LOS
AMI2_LOS
PBO_EN
Bit 2
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
-
-
-
MPU_SEL_CNFG[2:0]
AMI1_VIO
AMI1_VIO
HZ_EN
Bit 1
L
L
-
-
IN5_DIV[1:0]
FREQ_MO
AMI1_LOS
AMI1_LOS
N_HARD_
MS_SL_C
INT_POL
December 9, 2008
Bit 0
TRL
EN
WAN PLL
Reference
Page
P 71
P 72
P 72
P 73
P 74
P 74
P 75
P 76
P 77
P 77
P 78
P 79
P 79
P 80
P 81
P 82
P 83
P 84
P 85
P 86
P 87
P 88