IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 8

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23
Figure 5. External Fast Selection ................................................................................................................................................................................ 25
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 42
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 42
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 43
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 43
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 44
Figure 14. IDT82V3280 Power Decoupling Scheme ................................................................................................................................................... 46
Figure 15. Typical Application ...................................................................................................................................................................................... 47
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 49
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 50
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 51
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 52
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 53
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 54
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 55
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 56
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 56
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 57
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 58
Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 150
Figure 28. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 152
Figure 29. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 152
Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 152
Figure 31. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 152
Figure 32. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 153
Figure 33. Recommended PECL Input Port Line Termination .................................................................................................................................. 155
Figure 34. Recommended PECL Output Port Line Termination ................................................................................................................................ 155
Figure 35. Recommended LVDS Input Port Line Termination .................................................................................................................................. 157
Figure 36. Recommended LVDS Output Port Line Termination ................................................................................................................................ 157
Figure 37. Output Wander Generation ...................................................................................................................................................................... 161
Figure 38. Input / Output Clock Timing ...................................................................................................................................................................... 162
Figure 39. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 168
Figure 40. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 169
Figure 41. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 170
List of Figures
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December 9, 2008