IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 33

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

switched to another one’ - are: (The T0 selected input clock is disquali-
fied AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selec-
tion or Forced selection).
path.
3.9.2
T4_OPERATING_MODE[2:0] bits, as shown in
Table 16: T4 DPLL Operating Mode Control
the internal state machine is shown in
Functional Description
IDT82V3280
Figure 8. T4 Selected Input Clock vs. DPLL Automatic
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
Refer to
The
When the operating mode is switched automatically, the operation of
T4_OPERATING_MODE[2:0]
T4
T4 SELECTED INPUT CLOCK VS. DPLL OPERATING
MODE
Table 13
DPLL
000
001
010
100
3
for details about the input clock qualification for T0
1
operating
Operating Mode
Free-Run mode
Locked mode
Holdover
mode
2
5
mode
Figure
T4 DPLL Operating Mode
8:
Forced - Free-Run
is
Forced - Holdover
Forced - Locked
Table
Automatic
controlled
16:
4
by
the
33
path.
Table 17: Related Bit / Register in Chapter 3.9
T0_DPLL_OPERATING_MOD
T0_OPERATING_MODE[2:0]
T4_OPERATING_MODE[2:0]
T0_OPERATING_MODE
T0_OPERATING_MODE
Notes to
Refer to
1. Reset.
2. An input clock is selected.
3. (The T4 selected input clock is disqualified) OR (A qualified input
4. An input clock is selected.
5. No input clock is selected.
clock with a higher priority is switched to) OR (The T4 selected
input clock is switched to another one by Forced selection) OR
(When T4 DPLL locks to the T0 DPLL output, the T4 selected
input clock is switched by setting the T0_FOR_T4 bit).
T0_DPLL_LOCK
T0_FOR_T4
E[2:0]
Table 13
Figure
Bit
8:
for details about the input clock qualification for T4
1
2
INTERRUPTS2_ENABLE_CNFG
T0_OPERATING_MODE_CNFG
T4_OPERATING_MODE_CNFG
T4_INPUT_SEL_CNFG
INTERRUPTS2_STS
OPERATING_STS
Register
December 9, 2008
WAN PLL
Address
(Hex)
0E
53
54
52
51
11